idpf: add controlq init and reset checks (8077c727) · Commits · git / linux-net

drivers/net/ethernet/intel/idpf/Makefile

+7 −1

Original line number	Diff line number	Diff line
		@@ -6,4 +6,10 @@
		obj-$(CONFIG_IDPF) += idpf.o

		idpf-y := \
		idpf_main.o
		idpf_controlq.o \
		idpf_controlq_setup.o \
		idpf_dev.o \
		idpf_lib.o \
		idpf_main.o \
		idpf_virtchnl.o \
		idpf_vf_dev.o

drivers/net/ethernet/intel/idpf/idpf.h

+116 −0

Original line number	Diff line number	Diff line
		@@ -4,25 +4,141 @@
		#ifndef _IDPF_H_
		#define _IDPF_H_

		/* Forward declaration */
		struct idpf_adapter;

		#include <linux/aer.h>
		#include <linux/etherdevice.h>
		#include <linux/pci.h>

		#include "idpf_controlq.h"

		/* Default Mailbox settings */
		#define IDPF_NUM_DFLT_MBX_Q 2 /* includes both TX and RX */
		#define IDPF_DFLT_MBX_Q_LEN 64
		#define IDPF_DFLT_MBX_ID -1

		/* available message levels */
		#define IDPF_AVAIL_NETIF_M (NETIF_MSG_DRV \| NETIF_MSG_PROBE \| NETIF_MSG_LINK)

		/**
		* enum idpf_state - State machine to handle bring up
		* @__IDPF_STARTUP: Start the state machine
		* @__IDPF_STATE_LAST: Must be last, used to determine size
		*/
		enum idpf_state {
		__IDPF_STARTUP,
		__IDPF_STATE_LAST,
		};

		/**
		* enum idpf_flags - Hard reset causes.
		* @IDPF_HR_FUNC_RESET: Hard reset when TxRx timeout
		* @IDPF_HR_DRV_LOAD: Set on driver load for a clean HW
		* @IDPF_HR_RESET_IN_PROG: Reset in progress
		* @IDPF_REMOVE_IN_PROG: Driver remove in progress
		* @IDPF_FLAGS_NBITS: Must be last
		*/
		enum idpf_flags {
		IDPF_HR_FUNC_RESET,
		IDPF_HR_DRV_LOAD,
		IDPF_HR_RESET_IN_PROG,
		IDPF_REMOVE_IN_PROG,
		IDPF_FLAGS_NBITS,
		};

		/**
		* struct idpf_reset_reg - Reset register offsets/masks
		* @rstat: Reset status register
		* @rstat_m: Reset status mask
		*/
		struct idpf_reset_reg {
		void __iomem *rstat;
		u32 rstat_m;
		};

		/**
		* struct idpf_reg_ops - Device specific register operation function pointers
		* @ctlq_reg_init: Mailbox control queue register initialization
		* @reset_reg_init: Reset register initialization
		* @trigger_reset: Trigger a reset to occur
		*/
		struct idpf_reg_ops {
		void (ctlq_reg_init)(struct idpf_ctlq_create_info cq);
		void (reset_reg_init)(struct idpf_adapter adapter);
		void (trigger_reset)(struct idpf_adapter adapter,
		enum idpf_flags trig_cause);
		};

		/**
		* struct idpf_dev_ops - Device specific operations
		* @reg_ops: Register operations
		*/
		struct idpf_dev_ops {
		struct idpf_reg_ops reg_ops;
		};

		/**
		* struct idpf_adapter - Device data struct generated on probe
		* @pdev: PCI device struct given on probe
		* @msg_enable: Debug message level enabled
		* @state: Init state machine
		* @flags: See enum idpf_flags
		* @reset_reg: See struct idpf_reset_reg
		* @hw: Device access data
		* @vc_event_task: Task to handle out of band virtchnl event notifications
		* @vc_event_wq: Workqueue for virtchnl events
		* @dev_ops: See idpf_dev_ops
		* @vport_ctrl_lock: Lock to protect the vport control flow
		*/
		struct idpf_adapter {
		struct pci_dev *pdev;
		u32 msg_enable;
		enum idpf_state state;
		DECLARE_BITMAP(flags, IDPF_FLAGS_NBITS);
		struct idpf_reset_reg reset_reg;
		struct idpf_hw hw;

		struct delayed_work vc_event_task;
		struct workqueue_struct *vc_event_wq;

		struct idpf_dev_ops dev_ops;

		struct mutex vport_ctrl_lock;
		};

		/**
		* idpf_get_reg_addr - Get BAR0 register address
		* @adapter: private data struct
		* @reg_offset: register offset value
		*
		* Based on the register offset, return the actual BAR0 register address
		*/
		static inline void __iomem idpf_get_reg_addr(struct idpf_adapter adapter,
		resource_size_t reg_offset)
		{
		return (void __iomem *)(adapter->hw.hw_addr + reg_offset);
		}

		/**
		* idpf_is_reset_detected - check if we were reset at some point
		* @adapter: driver specific private structure
		*
		* Returns true if we are either in reset currently or were previously reset.
		*/
		static inline bool idpf_is_reset_detected(struct idpf_adapter *adapter)
		{
		if (!adapter->hw.arq)
		return true;

		return !(readl(idpf_get_reg_addr(adapter, adapter->hw.arq->reg.len)) &
		adapter->hw.arq->reg.len_mask);
		}

		void idpf_vc_event_task(struct work_struct *work);
		void idpf_dev_ops_init(struct idpf_adapter *adapter);
		void idpf_vf_dev_ops_init(struct idpf_adapter *adapter);
		int idpf_init_dflt_mbx(struct idpf_adapter *adapter);
		void idpf_deinit_dflt_mbx(struct idpf_adapter *adapter);

		#endif /* !_IDPF_H_ */

drivers/net/ethernet/intel/idpf/idpf_controlq.c

0 → 100644

+621 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/* Copyright (C) 2023 Intel Corporation */

		#include "idpf_controlq.h"

		/**
		* idpf_ctlq_setup_regs - initialize control queue registers
		* @cq: pointer to the specific control queue
		* @q_create_info: structs containing info for each queue to be initialized
		*/
		static void idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq,
		struct idpf_ctlq_create_info *q_create_info)
		{
		/* set control queue registers in our local struct */
		cq->reg.head = q_create_info->reg.head;
		cq->reg.tail = q_create_info->reg.tail;
		cq->reg.len = q_create_info->reg.len;
		cq->reg.bah = q_create_info->reg.bah;
		cq->reg.bal = q_create_info->reg.bal;
		cq->reg.len_mask = q_create_info->reg.len_mask;
		cq->reg.len_ena_mask = q_create_info->reg.len_ena_mask;
		cq->reg.head_mask = q_create_info->reg.head_mask;
		}

		/**
		* idpf_ctlq_init_regs - Initialize control queue registers
		* @hw: pointer to hw struct
		* @cq: pointer to the specific Control queue
		* @is_rxq: true if receive control queue, false otherwise
		*
		* Initialize registers. The caller is expected to have already initialized the
		* descriptor ring memory and buffer memory
		*/
		static void idpf_ctlq_init_regs(struct idpf_hw hw, struct idpf_ctlq_info cq,
		bool is_rxq)
		{
		/* Update tail to post pre-allocated buffers for rx queues */
		if (is_rxq)
		wr32(hw, cq->reg.tail, (u32)(cq->ring_size - 1));

		/* For non-Mailbox control queues only TAIL need to be set */
		if (cq->q_id != -1)
		return;

		/* Clear Head for both send or receive */
		wr32(hw, cq->reg.head, 0);

		/* set starting point */
		wr32(hw, cq->reg.bal, lower_32_bits(cq->desc_ring.pa));
		wr32(hw, cq->reg.bah, upper_32_bits(cq->desc_ring.pa));
		wr32(hw, cq->reg.len, (cq->ring_size \| cq->reg.len_ena_mask));
		}

		/**
		* idpf_ctlq_init_rxq_bufs - populate receive queue descriptors with buf
		* @cq: pointer to the specific Control queue
		*
		* Record the address of the receive queue DMA buffers in the descriptors.
		* The buffers must have been previously allocated.
		*/
		static void idpf_ctlq_init_rxq_bufs(struct idpf_ctlq_info *cq)
		{
		int i;

		for (i = 0; i < cq->ring_size; i++) {
		struct idpf_ctlq_desc *desc = IDPF_CTLQ_DESC(cq, i);
		struct idpf_dma_mem *bi = cq->bi.rx_buff[i];

		/* No buffer to post to descriptor, continue */
		if (!bi)
		continue;

		desc->flags =
		cpu_to_le16(IDPF_CTLQ_FLAG_BUF \| IDPF_CTLQ_FLAG_RD);
		desc->opcode = 0;
		desc->datalen = cpu_to_le16(bi->size);
		desc->ret_val = 0;
		desc->v_opcode_dtype = 0;
		desc->v_retval = 0;
		desc->params.indirect.addr_high =
		cpu_to_le32(upper_32_bits(bi->pa));
		desc->params.indirect.addr_low =
		cpu_to_le32(lower_32_bits(bi->pa));
		desc->params.indirect.param0 = 0;
		desc->params.indirect.sw_cookie = 0;
		desc->params.indirect.v_flags = 0;
		}
		}

		/**
		* idpf_ctlq_shutdown - shutdown the CQ
		* @hw: pointer to hw struct
		* @cq: pointer to the specific Control queue
		*
		* The main shutdown routine for any controq queue
		*/
		static void idpf_ctlq_shutdown(struct idpf_hw hw, struct idpf_ctlq_info cq)
		{
		mutex_lock(&cq->cq_lock);

		/* free ring buffers and the ring itself */
		idpf_ctlq_dealloc_ring_res(hw, cq);

		/* Set ring_size to 0 to indicate uninitialized queue */
		cq->ring_size = 0;

		mutex_unlock(&cq->cq_lock);
		mutex_destroy(&cq->cq_lock);
		}

		/**
		* idpf_ctlq_add - add one control queue
		* @hw: pointer to hardware struct
		* @qinfo: info for queue to be created
		* @cq_out: (output) double pointer to control queue to be created
		*
		* Allocate and initialize a control queue and add it to the control queue list.
		* The cq parameter will be allocated/initialized and passed back to the caller
		* if no errors occur.
		*
		* Note: idpf_ctlq_init must be called prior to any calls to idpf_ctlq_add
		*/
		int idpf_ctlq_add(struct idpf_hw *hw,
		struct idpf_ctlq_create_info *qinfo,
		struct idpf_ctlq_info **cq_out)
		{
		struct idpf_ctlq_info *cq;
		bool is_rxq = false;
		int err;

		cq = kzalloc(sizeof(*cq), GFP_KERNEL);
		if (!cq)
		return -ENOMEM;

		cq->cq_type = qinfo->type;
		cq->q_id = qinfo->id;
		cq->buf_size = qinfo->buf_size;
		cq->ring_size = qinfo->len;

		cq->next_to_use = 0;
		cq->next_to_clean = 0;
		cq->next_to_post = cq->ring_size - 1;

		switch (qinfo->type) {
		case IDPF_CTLQ_TYPE_MAILBOX_RX:
		is_rxq = true;
		fallthrough;
		case IDPF_CTLQ_TYPE_MAILBOX_TX:
		err = idpf_ctlq_alloc_ring_res(hw, cq);
		break;
		default:
		err = -EBADR;
		break;
		}

		if (err)
		goto init_free_q;

		if (is_rxq) {
		idpf_ctlq_init_rxq_bufs(cq);
		} else {
		/* Allocate the array of msg pointers for TX queues */
		cq->bi.tx_msg = kcalloc(qinfo->len,
		sizeof(struct idpf_ctlq_msg *),
		GFP_KERNEL);
		if (!cq->bi.tx_msg) {
		err = -ENOMEM;
		goto init_dealloc_q_mem;
		}
		}

		idpf_ctlq_setup_regs(cq, qinfo);

		idpf_ctlq_init_regs(hw, cq, is_rxq);

		mutex_init(&cq->cq_lock);

		list_add(&cq->cq_list, &hw->cq_list_head);

		*cq_out = cq;

		return 0;

		init_dealloc_q_mem:
		/* free ring buffers and the ring itself */
		idpf_ctlq_dealloc_ring_res(hw, cq);
		init_free_q:
		kfree(cq);

		return err;
		}

		/**
		* idpf_ctlq_remove - deallocate and remove specified control queue
		* @hw: pointer to hardware struct
		* @cq: pointer to control queue to be removed
		*/
		void idpf_ctlq_remove(struct idpf_hw *hw,
		struct idpf_ctlq_info *cq)
		{
		list_del(&cq->cq_list);
		idpf_ctlq_shutdown(hw, cq);
		kfree(cq);
		}

		/**
		* idpf_ctlq_init - main initialization routine for all control queues
		* @hw: pointer to hardware struct
		* @num_q: number of queues to initialize
		* @q_info: array of structs containing info for each queue to be initialized
		*
		* This initializes any number and any type of control queues. This is an all
		* or nothing routine; if one fails, all previously allocated queues will be
		* destroyed. This must be called prior to using the individual add/remove
		* APIs.
		*/
		int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q,
		struct idpf_ctlq_create_info *q_info)
		{
		struct idpf_ctlq_info cq, tmp;
		int err;
		int i;

		INIT_LIST_HEAD(&hw->cq_list_head);

		for (i = 0; i < num_q; i++) {
		struct idpf_ctlq_create_info *qinfo = q_info + i;

		err = idpf_ctlq_add(hw, qinfo, &cq);
		if (err)
		goto init_destroy_qs;
		}

		return 0;

		init_destroy_qs:
		list_for_each_entry_safe(cq, tmp, &hw->cq_list_head, cq_list)
		idpf_ctlq_remove(hw, cq);

		return err;
		}

		/**
		* idpf_ctlq_deinit - destroy all control queues
		* @hw: pointer to hw struct
		*/
		void idpf_ctlq_deinit(struct idpf_hw *hw)
		{
		struct idpf_ctlq_info cq, tmp;

		list_for_each_entry_safe(cq, tmp, &hw->cq_list_head, cq_list)
		idpf_ctlq_remove(hw, cq);
		}

		/**
		* idpf_ctlq_send - send command to Control Queue (CTQ)
		* @hw: pointer to hw struct
		* @cq: handle to control queue struct to send on
		* @num_q_msg: number of messages to send on control queue
		* @q_msg: pointer to array of queue messages to be sent
		*
		* The caller is expected to allocate DMAable buffers and pass them to the
		* send routine via the q_msg struct / control queue specific data struct.
		* The control queue will hold a reference to each send message until
		* the completion for that message has been cleaned.
		*/
		int idpf_ctlq_send(struct idpf_hw hw, struct idpf_ctlq_info cq,
		u16 num_q_msg, struct idpf_ctlq_msg q_msg[])
		{
		struct idpf_ctlq_desc *desc;
		int num_desc_avail;
		int err = 0;
		int i;

		mutex_lock(&cq->cq_lock);

		/* Ensure there are enough descriptors to send all messages */
		num_desc_avail = IDPF_CTLQ_DESC_UNUSED(cq);
		if (num_desc_avail == 0 \|\| num_desc_avail < num_q_msg) {
		err = -ENOSPC;
		goto err_unlock;
		}

		for (i = 0; i < num_q_msg; i++) {
		struct idpf_ctlq_msg *msg = &q_msg[i];

		desc = IDPF_CTLQ_DESC(cq, cq->next_to_use);

		desc->opcode = cpu_to_le16(msg->opcode);
		desc->pfid_vfid = cpu_to_le16(msg->func_id);

		desc->v_opcode_dtype = cpu_to_le32(msg->cookie.mbx.chnl_opcode);
		desc->v_retval = cpu_to_le32(msg->cookie.mbx.chnl_retval);

		desc->flags = cpu_to_le16((msg->host_id & IDPF_HOST_ID_MASK) <<
		IDPF_CTLQ_FLAG_HOST_ID_S);
		if (msg->data_len) {
		struct idpf_dma_mem *buff = msg->ctx.indirect.payload;

		desc->datalen \|= cpu_to_le16(msg->data_len);
		desc->flags \|= cpu_to_le16(IDPF_CTLQ_FLAG_BUF);
		desc->flags \|= cpu_to_le16(IDPF_CTLQ_FLAG_RD);

		/* Update the address values in the desc with the pa
		* value for respective buffer
		*/
		desc->params.indirect.addr_high =
		cpu_to_le32(upper_32_bits(buff->pa));
		desc->params.indirect.addr_low =
		cpu_to_le32(lower_32_bits(buff->pa));

		memcpy(&desc->params, msg->ctx.indirect.context,
		IDPF_INDIRECT_CTX_SIZE);
		} else {
		memcpy(&desc->params, msg->ctx.direct,
		IDPF_DIRECT_CTX_SIZE);
		}

		/* Store buffer info */
		cq->bi.tx_msg[cq->next_to_use] = msg;

		(cq->next_to_use)++;
		if (cq->next_to_use == cq->ring_size)
		cq->next_to_use = 0;
		}

		/* Force memory write to complete before letting hardware
		* know that there are new descriptors to fetch.
		*/
		dma_wmb();

		wr32(hw, cq->reg.tail, cq->next_to_use);

		err_unlock:
		mutex_unlock(&cq->cq_lock);

		return err;
		}

		/**
		* idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the
		* requested queue
		* @cq: pointer to the specific Control queue
		* @clean_count: (input\|output) number of descriptors to clean as input, and
		* number of descriptors actually cleaned as output
		* @msg_status: (output) pointer to msg pointer array to be populated; needs
		* to be allocated by caller
		*
		* Returns an array of message pointers associated with the cleaned
		* descriptors. The pointers are to the original ctlq_msgs sent on the cleaned
		* descriptors. The status will be returned for each; any messages that failed
		* to send will have a non-zero status. The caller is expected to free original
		* ctlq_msgs and free or reuse the DMA buffers.
		*/
		int idpf_ctlq_clean_sq(struct idpf_ctlq_info cq, u16 clean_count,
		struct idpf_ctlq_msg *msg_status[])
		{
		struct idpf_ctlq_desc *desc;
		u16 i, num_to_clean;
		u16 ntc, desc_err;

		if (*clean_count == 0)
		return 0;
		if (*clean_count > cq->ring_size)
		return -EBADR;

		mutex_lock(&cq->cq_lock);

		ntc = cq->next_to_clean;

		num_to_clean = *clean_count;

		for (i = 0; i < num_to_clean; i++) {
		/* Fetch next descriptor and check if marked as done */
		desc = IDPF_CTLQ_DESC(cq, ntc);
		if (!(le16_to_cpu(desc->flags) & IDPF_CTLQ_FLAG_DD))
		break;

		/* strip off FW internal code */
		desc_err = le16_to_cpu(desc->ret_val) & 0xff;

		msg_status[i] = cq->bi.tx_msg[ntc];
		msg_status[i]->status = desc_err;

		cq->bi.tx_msg[ntc] = NULL;

		/* Zero out any stale data */
		memset(desc, 0, sizeof(*desc));

		ntc++;
		if (ntc == cq->ring_size)
		ntc = 0;
		}

		cq->next_to_clean = ntc;

		mutex_unlock(&cq->cq_lock);

		/* Return number of descriptors actually cleaned */
		*clean_count = i;

		return 0;
		}

		/**
		* idpf_ctlq_post_rx_buffs - post buffers to descriptor ring
		* @hw: pointer to hw struct
		* @cq: pointer to control queue handle
		* @buff_count: (input\|output) input is number of buffers caller is trying to
		* return; output is number of buffers that were not posted
		* @buffs: array of pointers to dma mem structs to be given to hardware
		*
		* Caller uses this function to return DMA buffers to the descriptor ring after
		* consuming them; buff_count will be the number of buffers.
		*
		* Note: this function needs to be called after a receive call even
		* if there are no DMA buffers to be returned, i.e. buff_count = 0,
		* buffs = NULL to support direct commands
		*/
		int idpf_ctlq_post_rx_buffs(struct idpf_hw hw, struct idpf_ctlq_info cq,
		u16 buff_count, struct idpf_dma_mem *buffs)
		{
		struct idpf_ctlq_desc *desc;
		u16 ntp = cq->next_to_post;
		bool buffs_avail = false;
		u16 tbp = ntp + 1;
		int i = 0;

		if (*buff_count > cq->ring_size)
		return -EBADR;

		if (*buff_count > 0)
		buffs_avail = true;

		mutex_lock(&cq->cq_lock);

		if (tbp >= cq->ring_size)
		tbp = 0;

		if (tbp == cq->next_to_clean)
		/* Nothing to do */
		goto post_buffs_out;

		/* Post buffers for as many as provided or up until the last one used */
		while (ntp != cq->next_to_clean) {
		desc = IDPF_CTLQ_DESC(cq, ntp);

		if (cq->bi.rx_buff[ntp])
		goto fill_desc;
		if (!buffs_avail) {
		/* If the caller hasn't given us any buffers or
		* there are none left, search the ring itself
		* for an available buffer to move to this
		* entry starting at the next entry in the ring
		*/
		tbp = ntp + 1;

		/* Wrap ring if necessary */
		if (tbp >= cq->ring_size)
		tbp = 0;

		while (tbp != cq->next_to_clean) {
		if (cq->bi.rx_buff[tbp]) {
		cq->bi.rx_buff[ntp] =
		cq->bi.rx_buff[tbp];
		cq->bi.rx_buff[tbp] = NULL;

		/* Found a buffer, no need to
		* search anymore
		*/
		break;
		}

		/* Wrap ring if necessary */
		tbp++;
		if (tbp >= cq->ring_size)
		tbp = 0;
		}

		if (tbp == cq->next_to_clean)
		goto post_buffs_out;
		} else {
		/* Give back pointer to DMA buffer */
		cq->bi.rx_buff[ntp] = buffs[i];
		i++;

		if (i >= *buff_count)
		buffs_avail = false;
		}

		fill_desc:
		desc->flags =
		cpu_to_le16(IDPF_CTLQ_FLAG_BUF \| IDPF_CTLQ_FLAG_RD);

		/* Post buffers to descriptor */
		desc->datalen = cpu_to_le16(cq->bi.rx_buff[ntp]->size);
		desc->params.indirect.addr_high =
		cpu_to_le32(upper_32_bits(cq->bi.rx_buff[ntp]->pa));
		desc->params.indirect.addr_low =
		cpu_to_le32(lower_32_bits(cq->bi.rx_buff[ntp]->pa));

		ntp++;
		if (ntp == cq->ring_size)
		ntp = 0;
		}

		post_buffs_out:
		/* Only update tail if buffers were actually posted */
		if (cq->next_to_post != ntp) {
		if (ntp)
		/* Update next_to_post to ntp - 1 since current ntp
		* will not have a buffer
		*/
		cq->next_to_post = ntp - 1;
		else
		/* Wrap to end of end ring since current ntp is 0 */
		cq->next_to_post = cq->ring_size - 1;

		wr32(hw, cq->reg.tail, cq->next_to_post);
		}

		mutex_unlock(&cq->cq_lock);

		/* return the number of buffers that were not posted */
		buff_count = buff_count - i;

		return 0;
		}

		/**
		* idpf_ctlq_recv - receive control queue message call back
		* @cq: pointer to control queue handle to receive on
		* @num_q_msg: (input\|output) input number of messages that should be received;
		* output number of messages actually received
		* @q_msg: (output) array of received control queue messages on this q;
		* needs to be pre-allocated by caller for as many messages as requested
		*
		* Called by interrupt handler or polling mechanism. Caller is expected
		* to free buffers
		*/
		int idpf_ctlq_recv(struct idpf_ctlq_info cq, u16 num_q_msg,
		struct idpf_ctlq_msg *q_msg)
		{
		u16 num_to_clean, ntc, flags;
		struct idpf_ctlq_desc *desc;
		int err = 0;
		u16 i;

		if (*num_q_msg == 0)
		return 0;
		else if (*num_q_msg > cq->ring_size)
		return -EBADR;

		/* take the lock before we start messing with the ring */
		mutex_lock(&cq->cq_lock);

		ntc = cq->next_to_clean;

		num_to_clean = *num_q_msg;

		for (i = 0; i < num_to_clean; i++) {
		/* Fetch next descriptor and check if marked as done */
		desc = IDPF_CTLQ_DESC(cq, ntc);
		flags = le16_to_cpu(desc->flags);

		if (!(flags & IDPF_CTLQ_FLAG_DD))
		break;

		q_msg[i].vmvf_type = (flags &
		(IDPF_CTLQ_FLAG_FTYPE_VM \|
		IDPF_CTLQ_FLAG_FTYPE_PF)) >>
		IDPF_CTLQ_FLAG_FTYPE_S;

		if (flags & IDPF_CTLQ_FLAG_ERR)
		err = -EBADMSG;

		q_msg[i].cookie.mbx.chnl_opcode =
		le32_to_cpu(desc->v_opcode_dtype);
		q_msg[i].cookie.mbx.chnl_retval =
		le32_to_cpu(desc->v_retval);

		q_msg[i].opcode = le16_to_cpu(desc->opcode);
		q_msg[i].data_len = le16_to_cpu(desc->datalen);
		q_msg[i].status = le16_to_cpu(desc->ret_val);

		if (desc->datalen) {
		memcpy(q_msg[i].ctx.indirect.context,
		&desc->params.indirect, IDPF_INDIRECT_CTX_SIZE);

		/* Assign pointer to dma buffer to ctlq_msg array
		* to be given to upper layer
		*/
		q_msg[i].ctx.indirect.payload = cq->bi.rx_buff[ntc];

		/* Zero out pointer to DMA buffer info;
		* will be repopulated by post buffers API
		*/
		cq->bi.rx_buff[ntc] = NULL;
		} else {
		memcpy(q_msg[i].ctx.direct, desc->params.raw,
		IDPF_DIRECT_CTX_SIZE);
		}

		/* Zero out stale data in descriptor */
		memset(desc, 0, sizeof(struct idpf_ctlq_desc));

		ntc++;
		if (ntc == cq->ring_size)
		ntc = 0;
		}

		cq->next_to_clean = ntc;

		mutex_unlock(&cq->cq_lock);

		*num_q_msg = i;
		if (*num_q_msg == 0)
		err = -ENOMSG;

		return err;
		}

drivers/net/ethernet/intel/idpf/idpf_controlq.h

+116 −0

Original line number	Diff line number	Diff line
		@@ -4,11 +4,127 @@
		#ifndef _IDPF_CONTROLQ_H_
		#define _IDPF_CONTROLQ_H_

		#include <linux/slab.h>

		#include "idpf_controlq_api.h"

		/* Maximum buffer length for all control queue types */
		#define IDPF_CTLQ_MAX_BUF_LEN 4096

		#define IDPF_CTLQ_DESC(R, i) \
		(&(((struct idpf_ctlq_desc *)((R)->desc_ring.va))[i]))

		#define IDPF_CTLQ_DESC_UNUSED(R) \
		((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->ring_size) + \
		(R)->next_to_clean - (R)->next_to_use - 1))

		/* Control Queue default settings */
		#define IDPF_CTRL_SQ_CMD_TIMEOUT 250 /* msecs */

		struct idpf_ctlq_desc {
		/* Control queue descriptor flags */
		__le16 flags;
		/* Control queue message opcode */
		__le16 opcode;
		__le16 datalen; /* 0 for direct commands */
		union {
		__le16 ret_val;
		__le16 pfid_vfid;
		#define IDPF_CTLQ_DESC_VF_ID_S 0
		#define IDPF_CTLQ_DESC_VF_ID_M (0x7FF << IDPF_CTLQ_DESC_VF_ID_S)
		#define IDPF_CTLQ_DESC_PF_ID_S 11
		#define IDPF_CTLQ_DESC_PF_ID_M (0x1F << IDPF_CTLQ_DESC_PF_ID_S)
		};

		/* Virtchnl message opcode and virtchnl descriptor type
		* v_opcode=[27:0], v_dtype=[31:28]
		*/
		__le32 v_opcode_dtype;
		/* Virtchnl return value */
		__le32 v_retval;
		union {
		struct {
		__le32 param0;
		__le32 param1;
		__le32 param2;
		__le32 param3;
		} direct;
		struct {
		__le32 param0;
		__le16 sw_cookie;
		/* Virtchnl flags */
		__le16 v_flags;
		__le32 addr_high;
		__le32 addr_low;
		} indirect;
		u8 raw[16];
		} params;
		};

		/* Flags sub-structure
		* \|0 \|1 \|2 \|3 \|4 \|5 \|6 \|7 \|8 \|9 \|10 \|11 \|12 \|13 \|14 \|15 \|
		* \|DD \|CMP\|ERR\| * RSV * \|FTYPE \| RSV \|RD \|VFC\|BUF\| HOST_ID \|
		*/
		/* command flags and offsets */
		#define IDPF_CTLQ_FLAG_DD_S 0
		#define IDPF_CTLQ_FLAG_CMP_S 1
		#define IDPF_CTLQ_FLAG_ERR_S 2
		#define IDPF_CTLQ_FLAG_FTYPE_S 6
		#define IDPF_CTLQ_FLAG_RD_S 10
		#define IDPF_CTLQ_FLAG_VFC_S 11
		#define IDPF_CTLQ_FLAG_BUF_S 12
		#define IDPF_CTLQ_FLAG_HOST_ID_S 13

		#define IDPF_CTLQ_FLAG_DD BIT(IDPF_CTLQ_FLAG_DD_S) /* 0x1 */
		#define IDPF_CTLQ_FLAG_CMP BIT(IDPF_CTLQ_FLAG_CMP_S) /* 0x2 */
		#define IDPF_CTLQ_FLAG_ERR BIT(IDPF_CTLQ_FLAG_ERR_S) /* 0x4 */
		#define IDPF_CTLQ_FLAG_FTYPE_VM BIT(IDPF_CTLQ_FLAG_FTYPE_S) /* 0x40 */
		#define IDPF_CTLQ_FLAG_FTYPE_PF BIT(IDPF_CTLQ_FLAG_FTYPE_S + 1) /* 0x80 */
		#define IDPF_CTLQ_FLAG_RD BIT(IDPF_CTLQ_FLAG_RD_S) /* 0x400 */
		#define IDPF_CTLQ_FLAG_VFC BIT(IDPF_CTLQ_FLAG_VFC_S) /* 0x800 */
		#define IDPF_CTLQ_FLAG_BUF BIT(IDPF_CTLQ_FLAG_BUF_S) /* 0x1000 */

		/* Host ID is a special field that has 3b and not a 1b flag */
		#define IDPF_CTLQ_FLAG_HOST_ID_M MAKE_MASK(0x7000UL, IDPF_CTLQ_FLAG_HOST_ID_S)

		struct idpf_mbxq_desc {
		u8 pad[8]; /* CTLQ flags/opcode/len/retval fields */
		u32 chnl_opcode; /* avoid confusion with desc->opcode */
		u32 chnl_retval; /* ditto for desc->retval */
		u32 pf_vf_id; /* used by CP when sending to PF */
		};

		/* Define the driver hardware struct to replace other control structs as needed
		* Align to ctlq_hw_info
		*/
		struct idpf_hw {
		void __iomem *hw_addr;
		resource_size_t hw_addr_len;

		struct idpf_adapter *back;

		/* control queue - send and receive */
		struct idpf_ctlq_info *asq;
		struct idpf_ctlq_info *arq;

		/* pci info */
		u16 device_id;
		u16 vendor_id;
		u16 subsystem_device_id;
		u16 subsystem_vendor_id;
		u8 revision_id;
		bool adapter_stopped;

		struct list_head cq_list_head;
		};

		int idpf_ctlq_alloc_ring_res(struct idpf_hw *hw,
		struct idpf_ctlq_info *cq);

		void idpf_ctlq_dealloc_ring_res(struct idpf_hw hw, struct idpf_ctlq_info cq);

		/* prototype for functions used for dynamic memory allocation */
		void idpf_alloc_dma_mem(struct idpf_hw hw, struct idpf_dma_mem *mem,
		u64 size);
		void idpf_free_dma_mem(struct idpf_hw hw, struct idpf_dma_mem mem);
		#endif /* _IDPF_CONTROLQ_H_ */

drivers/net/ethernet/intel/idpf/idpf_controlq_api.h

0 → 100644

+169 −0

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