Commit 807e5d38 authored by Huacai Chen's avatar Huacai Chen
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LoongArch: Complete CPUCFG registers definition 



According to the "LoongArch Reference Manual Volume 1: Basic
Architecture", begin with LA664 CPU core there are more features
supported which are indicated in CPUCFG2 and CPUCFG3. This patch
completes the definitions of them so as to match the architecture
specification.

Signed-off-by: default avatarBibo Mao <maobibo@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent f8f9c1f4

arch/loongarch/include/asm/loongarch.h

+7 −0
Original line number Diff line number Diff line
@@ -94,6 +94,12 @@ 
#define  CPUCFG2_LSPW			BIT(21)

#define  CPUCFG2_LAM			BIT(22)

#define  CPUCFG2_PTW			BIT(24)

#define  CPUCFG2_FRECIPE		BIT(25)

#define  CPUCFG2_DIV32			BIT(26)

#define  CPUCFG2_LAM_BH			BIT(27)

#define  CPUCFG2_LAMCAS			BIT(28)

#define  CPUCFG2_LLACQ_SCREL		BIT(29)

#define  CPUCFG2_SCQ			BIT(30)



#define LOONGARCH_CPUCFG3		0x3

#define  CPUCFG3_CCDMA			BIT(0)
@@ -108,6 +114,7 @@ 
#define  CPUCFG3_SPW_HG_HF		BIT(11)

#define  CPUCFG3_RVA			BIT(12)

#define  CPUCFG3_RVAMAX			GENMASK(16, 13)

#define  CPUCFG3_DBAR_HINTS		BIT(17)

#define  CPUCFG3_ALDORDER_CAP		BIT(18) /* All address load ordered, capability */

#define  CPUCFG3_ASTORDER_CAP		BIT(19) /* All address store ordered, capability */

#define  CPUCFG3_ALDORDER_STA		BIT(20) /* All address load ordered, status */