Commit 80809c91 authored by Uma Shankar's avatar Uma Shankar
Browse files

drm/i915: Remove i915_reg.h from intel_modeset_setup.c 



Move GEN9_CLKGATE_DIS_0 reg to display header to make
intel_modeset_setup.c free from i915_reg.h include.

v2: Remove from gmd common header and use display_regs.h (Jani)

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-20-uma.shankar@intel.com
parent b4c9ae4e

drivers/gpu/drm/i915/display/intel_display_regs.h

+14 −0
Original line number Diff line number Diff line
@@ -407,6 +407,20 @@ 
#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)

#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)



/*

 * GEN9 clock gating regs

 */

#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)

#define   DARBF_GATING_DIS		REG_BIT(27)

#define   DMG_GATING_DIS		REG_BIT(21)

#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))

#define   PWM2_GATING_DIS		REG_BIT(14)

#define   PWM1_GATING_DIS		REG_BIT(13)



#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)

#define   TGL_VRH_GATING_DIS		REG_BIT(31)

#define   DPT_GATING_DIS		REG_BIT(22)



#define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)

#define   BXT_GMBUS_GATING_DIS		(1 << 14)

#define   DG2_DPFC_GATING_DIS		REG_BIT(31)

drivers/gpu/drm/i915/display/intel_modeset_setup.c

+0 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 
#include <drm/drm_print.h>

#include <drm/drm_vblank.h>



#include "i915_reg.h"

#include "i9xx_wm.h"

#include "intel_atomic.h"

#include "intel_bw.h"

drivers/gpu/drm/i915/i915_reg.h

+0 −14
Original line number Diff line number Diff line
@@ -630,20 +630,6 @@ 
#define VLV_CLK_CTL2			_MMIO(0x101104)

#define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28



/*

 * GEN9 clock gating regs

 */

#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)

#define   DARBF_GATING_DIS		REG_BIT(27)

#define   DMG_GATING_DIS		REG_BIT(21)

#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))

#define   PWM2_GATING_DIS		REG_BIT(14)

#define   PWM1_GATING_DIS		REG_BIT(13)



#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)

#define   TGL_VRH_GATING_DIS		REG_BIT(31)

#define   DPT_GATING_DIS		REG_BIT(22)



#define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)

#define   PIPEB_LINE_COMPARE_INT_EN			REG_BIT(29)

#define   PIPEB_HLINE_INT_EN			REG_BIT(28)