Commit 808e6530 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift



For the clksel clocks we are still using the legacy ti,bit-shift property
instead of the standard reg property. We can now use the reg property, so
let's do that for the clksel clocks.

To add the reg property, we switch to use #address-cells = <1>.

For now let's not update the clock-dss-tv-fck as it seems to share the same
register bit as the clock-dss-96m-fck and would introduce more warnings.

Cc: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 579856ae
Loading
Loading
Loading
Loading
+10 −8
Original line number Diff line number Diff line
@@ -66,22 +66,23 @@ clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		ipss_ick: clock-ipss-ick {
		ipss_ick: clock-ipss-ick@4 {
			reg = <4>;
			#clock-cells = <0>;
			compatible = "ti,am35xx-interface-clock";
			clock-output-names = "ipss_ick";
			clocks = <&core_l3_ick>;
			ti,bit-shift = <4>;
		};

		uart4_ick_am35xx: clock-uart4-ick-am35xx {
		uart4_ick_am35xx: clock-uart4-ick-am35xx@23 {
			reg = <23>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "uart4_ick_am35xx";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <23>;
		};
	};

@@ -101,14 +102,15 @@ clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		uart4_fck_am35xx: clock-uart4-fck-am35xx {
		uart4_fck_am35xx: clock-uart4-fck-am35xx@23 {
			reg = <23>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart4_fck_am35xx";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <23>;
		};
	};
};
+28 −24
Original line number Diff line number Diff line
@@ -50,30 +50,31 @@ clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		d2d_26m_fck: clock-d2d-26m-fck {
		d2d_26m_fck: clock-d2d-26m-fck@3 {
			reg = <3>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "d2d_26m_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <3>;
		};

		fshostusb_fck: clock-fshostusb-fck {
		fshostusb_fck: clock-fshostusb-fck@5 {
			reg = <5>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "fshostusb_fck";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <5>;
		};

		ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
		ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
			reg = <0>;
			#clock-cells = <0>;
			compatible = "ti,composite-no-wait-gate-clock";
			clock-output-names = "ssi_ssr_gate_fck_3430es1";
			clocks = <&corex2_fck>;
			ti,bit-shift = <0>;
		};
	};

@@ -81,23 +82,24 @@ clock@a40 {
		compatible = "ti,clksel";
		reg = <0xa40>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
		ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
			reg = <8>;
			#clock-cells = <0>;
			compatible = "ti,composite-divider-clock";
			clock-output-names = "ssi_ssr_div_fck_3430es1";
			clocks = <&corex2_fck>;
			ti,bit-shift = <8>;
			ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
		};

		usb_l4_div_ick: clock-usb-l4-div-ick {
		usb_l4_div_ick: clock-usb-l4-div-ick@4 {
			reg = <4>;
			#clock-cells = <0>;
			compatible = "ti,composite-divider-clock";
			clock-output-names = "usb_l4_div_ick";
			clocks = <&l4_ick>;
			ti,bit-shift = <4>;
			ti,max-div = <1>;
			ti,index-starts-at-one;
		};
@@ -121,38 +123,39 @@ clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
		hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
			reg = <4>;
			#clock-cells = <0>;
			compatible = "ti,omap3-no-wait-interface-clock";
			clock-output-names = "hsotgusb_ick_3430es1";
			clocks = <&core_l3_ick>;
			ti,bit-shift = <4>;
		};

		fac_ick: clock-fac-ick {
		fac_ick: clock-fac-ick@8 {
			reg = <8>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "fac_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <8>;
		};

		ssi_ick: clock-ssi-ick-3430es1 {
		ssi_ick: clock-ssi-ick-3430es1@0 {
			reg = <0>;
			#clock-cells = <0>;
			compatible = "ti,omap3-no-wait-interface-clock";
			clock-output-names = "ssi_ick_3430es1";
			clocks = <&ssi_l4_ick>;
			ti,bit-shift = <0>;
		};

		usb_l4_gate_ick: clock-usb-l4-gate-ick {
		usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
			reg = <5>;
			#clock-cells = <0>;
			compatible = "ti,composite-interface-clock";
			clock-output-names = "usb_l4_gate_ick";
			clocks = <&l4_ick>;
			ti,bit-shift = <5>;
		};
	};

@@ -174,14 +177,15 @@ clock@e00 {
		compatible = "ti,clksel";
		reg = <0xe00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
		dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
			reg = <0>;
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "dss1_alwon_fck_3430es1";
			clocks = <&dpll4_m4x2_ck>;
			ti,bit-shift = <0>;
			ti,set-rate-parent;
		};
	};
+46 −40
Original line number Diff line number Diff line
@@ -17,46 +17,47 @@ clock@a14 {
		compatible = "ti,clksel";
		reg = <0xa14>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		aes1_ick: clock-aes1-ick {
		aes1_ick: clock-aes1-ick@3 {
			reg = <3>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "aes1_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <3>;
		};

		rng_ick: clock-rng-ick {
		rng_ick: clock-rng-ick@2 {
			reg = <2>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "rng_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <2>;
		};

		sha11_ick: clock-sha11-ick {
		sha11_ick: clock-sha11-ick@1 {
			reg = <1>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "sha11_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <1>;
		};

		des1_ick: clock-des1-ick {
		des1_ick: clock-des1-ick@0 {
			reg = <0>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "des1_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <0>;
		};

		pka_ick: clock-pka-ick {
		pka_ick: clock-pka-ick@4 {
			reg = <4>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "pka_ick";
			clocks = <&security_l3_ick>;
			ti,bit-shift = <4>;
		};
	};

@@ -65,23 +66,24 @@ clock@f00 {
		compatible = "ti,clksel";
		reg = <0xf00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		cam_mclk: clock-cam-mclk {
		cam_mclk: clock-cam-mclk@0 {
			reg = <0>;
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "cam_mclk";
			clocks = <&dpll4_m5x2_ck>;
			ti,bit-shift = <0>;
			ti,set-rate-parent;
		};

		csi2_96m_fck: clock-csi2-96m-fck {
		csi2_96m_fck: clock-csi2-96m-fck@1 {
			reg = <1>;
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "csi2_96m_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <1>;
		};
	};

@@ -105,46 +107,47 @@ clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		icr_ick: clock-icr-ick {
		icr_ick: clock-icr-ick@29 {
			reg = <29>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "icr_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <29>;
		};

		des2_ick: clock-des2-ick {
		des2_ick: clock-des2-ick@26 {
			reg = <26>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "des2_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <26>;
		};

		mspro_ick: clock-mspro-ick {
		mspro_ick: clock-mspro-ick@23 {
			reg = <23>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mspro_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <23>;
		};

		mailboxes_ick: clock-mailboxes-ick {
		mailboxes_ick: clock-mailboxes-ick@7 {
			reg = <7>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mailboxes_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <7>;
		};

		sad2d_ick: clock-sad2d-ick {
		sad2d_ick: clock-sad2d-ick@3 {
			reg = <3>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "sad2d_ick";
			clocks = <&l3_ick>;
			ti,bit-shift = <3>;
		};
	};

@@ -160,22 +163,23 @@ clock@c00 {
		compatible = "ti,clksel";
		reg = <0xc00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		sr1_fck: clock-sr1-fck {
		sr1_fck: clock-sr1-fck@6 {
			reg = <6>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "sr1_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <6>;
		};

		sr2_fck: clock-sr2-fck {
		sr2_fck: clock-sr2-fck@7 {
			reg = <7>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "sr2_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <7>;
		};
	};

@@ -228,22 +232,23 @@ clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		modem_fck: clock-modem-fck {
		modem_fck: clock-modem-fck@31 {
			reg = <31>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "modem_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <31>;
		};

		mspro_fck: clock-mspro-fck {
		mspro_fck: clock-mspro-fck@23 {
			reg = <23>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mspro_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <23>;
		};
	};

@@ -252,14 +257,15 @@ clock@a18 {
		compatible = "ti,clksel";
		reg = <0xa18>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#ssize-cells = <0>;

		mad2d_ick: clock-mad2d-ick {
		mad2d_ick: clock-mad2d-ick@3 {
			reg = <3>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mad2d_ick";
			clocks = <&l3_ick>;
			ti,bit-shift = <3>;
		};
	};

+16 −12
Original line number Diff line number Diff line
@@ -138,14 +138,15 @@ clock@a18 {
		compatible = "ti,clksel";
		reg = <0xa18>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		usbtll_ick: clock-usbtll-ick {
		usbtll_ick: clock-usbtll-ick@2 {
			reg = <2>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "usbtll_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <2>;
		};
	};

@@ -153,14 +154,15 @@ clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		mmchs3_ick: clock-mmchs3-ick {
		mmchs3_ick: clock-mmchs3-ick@30 {
			reg = <30>;
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mmchs3_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <30>;
		};
	};

@@ -168,14 +170,15 @@ clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		mmchs3_fck: clock-mmchs3-fck {
		mmchs3_fck: clock-mmchs3-fck@30 {
			reg = <30>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mmchs3_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <30>;
		};
	};

@@ -183,14 +186,15 @@ clock@e00 {
		compatible = "ti,clksel";
		reg = <0xe00>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
		dss1_alwon_fck: clock-dss1-alwon-fck-3430es2@0 {
			reg = <0>;
			#clock-cells = <0>;
			compatible = "ti,dss-gate-clock";
			clock-output-names = "dss1_alwon_fck_3430es2";
			clocks = <&dpll4_m4x2_ck>;
			ti,bit-shift = <0>;
			ti,set-rate-parent;
		};
	};
+4 −3
Original line number Diff line number Diff line
@@ -62,14 +62,15 @@ clock@1000 {
		compatible = "ti,clksel";
		reg = <0x1000>;
		#clock-cells = <2>;
		#address-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		uart4_fck: clock-uart4-fck {
		uart4_fck: clock-uart4-fck@18 {
			reg = <18>;
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart4_fck";
			clocks = <&per_48m_fck>;
			ti,bit-shift = <18>;
		};
	};
};
Loading