Commit 8093383a authored by Victor Lu's avatar Victor Lu Committed by Alex Deucher
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drm/amdgpu: Improve error checking in amdgpu_virt_rlcg_reg_rw (v2)



The current error detection only looks for a timeout.
This should be changed to also check scratch_reg1 for any errors
returned from RLCG.

v2: remove new error value

Signed-off-by: default avatarVictor Lu <victorchengchi.lu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d6a76c0a
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+3 −2
Original line number Diff line number Diff line
@@ -979,7 +979,7 @@ u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 f
		 * SCRATCH_REG0 	= read/write value
		 * SCRATCH_REG1[30:28]	= command
		 * SCRATCH_REG1[19:0]	= address in dword
		 * SCRATCH_REG1[26:24]	= Error reporting
		 * SCRATCH_REG1[27:24]	= Error reporting
		 */
		writel(v, scratch_reg0);
		writel((offset | flag), scratch_reg1);
@@ -993,7 +993,8 @@ u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 f
			udelay(10);
		}

		if (i >= timeout) {
		tmp = readl(scratch_reg1);
		if (i >= timeout || (tmp & AMDGPU_RLCG_SCRATCH1_ERROR_MASK) != 0) {
			if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {
				if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
					dev_err(adev->dev,
+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@
#define AMDGPU_RLCG_REG_NOT_IN_RANGE		0x1000000

#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK	0xFFFFF
#define AMDGPU_RLCG_SCRATCH1_ERROR_MASK	0xF000000

/* all asic after AI use this offset */
#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5