Commit 80a4441c authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/sky1' 

- Add module support for platform controller driver (Manikandan K Pillai)

- Split headers into 'legacy' (LGA) and 'high perf' (HPA) (Manikandan K
  Pillai)

- Add DT binding and driver for CIX Sky1 (Hans Zhang)

* pci/controller/sky1:
  MAINTAINERS: Add CIX Sky1 PCIe controller driver maintainer
  PCI: sky1: Add PCIe host support for CIX Sky1
  dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings
  PCI: cadence: Add support for High Perf Architecture (HPA) controller
  PCI: cadence: Move PCIe RP common functions to a separate file
  PCI: cadence: Split PCIe controller header file
  PCI: cadence: Add module support for platform controller driver
parents af257c73 51f38bef

Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: CIX Sky1 PCIe Root Complex



maintainers:

  - Hans Zhang <hans.zhang@cixtech.com>



description:

  PCIe root complex controller based on the Cadence PCIe core.



allOf:

  - $ref: /schemas/pci/pci-host-bridge.yaml#



properties:

  compatible:

    const: cix,sky1-pcie-host



  reg:

    items:

      - description: PCIe controller registers.

      - description: ECAM registers.

      - description: Remote CIX System Unit strap registers.

      - description: Remote CIX System Unit status registers.

      - description: Region for sending messages registers.



  reg-names:

    items:

      - const: reg

      - const: cfg

      - const: rcsu_strap

      - const: rcsu_status

      - const: msg



  ranges:

    maxItems: 3



required:

  - compatible

  - ranges

  - bus-range

  - device_type

  - interrupt-map

  - interrupt-map-mask

  - msi-map



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@a010000 {

            compatible = "cix,sky1-pcie-host";

            reg = <0x00 0x0a010000 0x00 0x10000>,

                  <0x00 0x2c000000 0x00 0x4000000>,

                  <0x00 0x0a000300 0x00 0x100>,

                  <0x00 0x0a000400 0x00 0x100>,

                  <0x00 0x60000000 0x00 0x00100000>;

            reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";

            ranges = <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x00100000>,

                     <0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe00000>,

                     <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;

            #address-cells = <3>;

            #size-cells = <2>;

            bus-range = <0xc0 0xff>;

            device_type = "pci";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,

                            <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,

                            <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,

                            <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;

            msi-map = <0xc000 &gic_its 0xc000 0x4000>;

        };

    };

MAINTAINERS

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@@ -19630,6 +19630,13 @@ S: Orphan 
F:	Documentation/devicetree/bindings/pci/cdns,*

F:	drivers/pci/controller/cadence/*cadence*









PCI DRIVER FOR CIX Sky1









M:	Hans Zhang <hans.zhang@cixtech.com>









L:	linux-pci@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml









F:	drivers/pci/controller/cadence/*sky1*

















PCI DRIVER FOR FREESCALE LAYERSCAPE









M:	Minghuan Lian <minghuan.Lian@nxp.com>









M:	Mingkai Hu <mingkai.hu@nxp.com>

























drivers/pci/controller/cadence/Kconfig



+18
−3






























Original line number
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Diff line







@@ -19,10 +19,10 @@ config PCIE_CADENCE_EP







	select PCIE_CADENCE



















config PCIE_CADENCE_PLAT









	bool









	tristate



















config PCIE_CADENCE_PLAT_HOST









	bool "Cadence platform PCIe controller (host mode)"









	tristate "Cadence platform PCIe controller (host mode)"









	depends on OF









	select PCIE_CADENCE_HOST









	select PCIE_CADENCE_PLAT








@@ -32,7 +32,7 @@ config PCIE_CADENCE_PLAT_HOST







	  vendors SoCs.



















config PCIE_CADENCE_PLAT_EP









	bool "Cadence platform PCIe controller (endpoint mode)"









	tristate "Cadence platform PCIe controller (endpoint mode)"









	depends on OF









	depends on PCI_ENDPOINT









	select PCIE_CADENCE_EP








@@ -42,6 +42,21 @@ config PCIE_CADENCE_PLAT_EP







	  endpoint mode. This PCIe controller may be embedded into many









	  different vendors SoCs.



















config PCI_SKY1_HOST









	tristate "CIX SKY1 PCIe controller (host mode)"









	depends on OF && (ARCH_CIX || COMPILE_TEST)









	select PCIE_CADENCE_HOST









	select PCI_ECAM









	help









	  Say Y here if you want to support the CIX SKY1 PCIe platform









	  controller in host mode. CIX SKY1 PCIe controller uses Cadence









	  HPA (High Performance Architecture IP [Second generation of









	  Cadence PCIe IP])



















	  This driver requires Cadence PCIe core infrastructure









	  (PCIE_CADENCE_HOST) and hardware platform adaptation layer









	  to function.



















config PCIE_SG2042_HOST









	tristate "Sophgo SG2042 PCIe controller (host mode)"









	depends on OF && (ARCH_SOPHGO || COMPILE_TEST)
































drivers/pci/controller/cadence/Makefile



+8
−3






























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Diff line









# SPDX-License-Identifier: GPL-2.0









obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o









obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o









obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o









pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o









pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o









pcie-cadence-ep-mod-y := pcie-cadence-ep.o



















obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o









obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o









obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o









obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o









obj-$(CONFIG_PCI_J721E) += pci-j721e.o









obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o









obj-$(CONFIG_PCI_SKY1_HOST) += pci-sky1.o
























drivers/pci/controller/cadence/pci-sky1.c
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+238
−0






























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// SPDX-License-Identifier: GPL-2.0









/*









 * PCIe controller driver for CIX's sky1 SoCs









 *









 * Copyright 2025 Cix Technology Group Co., Ltd.









 * Author: Hans Zhang <hans.zhang@cixtech.com>









 */



















#include <linux/kernel.h>









#include <linux/module.h>









#include <linux/of.h>









#include <linux/of_device.h>









#include <linux/pci.h>









#include <linux/pci-ecam.h>









#include <linux/pci_ids.h>



















#include "pcie-cadence.h"









#include "pcie-cadence-host-common.h"



















#define PCI_VENDOR_ID_CIX		0x1f6c









#define PCI_DEVICE_ID_CIX_SKY1		0x0001



















#define STRAP_REG(n)			((n) * 0x04)









#define STATUS_REG(n)			((n) * 0x04)









#define LINK_TRAINING_ENABLE		BIT(0)









#define LINK_COMPLETE			BIT(0)



















#define SKY1_IP_REG_BANK		0x1000









#define SKY1_IP_CFG_CTRL_REG_BANK	0x4c00









#define SKY1_IP_AXI_MASTER_COMMON	0xf000









#define SKY1_AXI_SLAVE			0x9000









#define SKY1_AXI_MASTER			0xb000









#define SKY1_AXI_HLS_REGISTERS		0xc000









#define SKY1_AXI_RAS_REGISTERS		0xe000









#define SKY1_DTI_REGISTERS		0xd000



















#define IP_REG_I_DBG_STS_0		0x420



















struct sky1_pcie {









	struct cdns_pcie *cdns_pcie;









	struct cdns_pcie_rc *cdns_pcie_rc;



















	struct resource *cfg_res;









	struct resource *msg_res;









	struct pci_config_window *cfg;









	void __iomem *strap_base;









	void __iomem *status_base;









	void __iomem *reg_base;









	void __iomem *cfg_base;









	void __iomem *msg_base;









};



















static int sky1_pcie_resource_get(struct platform_device *pdev,









				  struct sky1_pcie *pcie)









{









	struct device *dev = &pdev->dev;









	struct resource *res;









	void __iomem *base;



















	base = devm_platform_ioremap_resource_byname(pdev, "reg");









	if (IS_ERR(base))









		return dev_err_probe(dev, PTR_ERR(base),









				     "unable to find \"reg\" registers\n");









	pcie->reg_base = base;



















	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");









	if (!res)









		return dev_err_probe(dev, -ENODEV, "unable to get \"cfg\" resource\n");









	pcie->cfg_res = res;



















	base = devm_platform_ioremap_resource_byname(pdev, "rcsu_strap");









	if (IS_ERR(base))









		return dev_err_probe(dev, PTR_ERR(base),









				     "unable to find \"rcsu_strap\" registers\n");









	pcie->strap_base = base;



















	base = devm_platform_ioremap_resource_byname(pdev, "rcsu_status");









	if (IS_ERR(base))









		return dev_err_probe(dev, PTR_ERR(base),









				     "unable to find \"rcsu_status\" registers\n");









	pcie->status_base = base;



















	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg");









	if (!res)









		return dev_err_probe(dev, -ENODEV, "unable to get \"msg\" resource\n");









	pcie->msg_res = res;









	pcie->msg_base = devm_ioremap_resource(dev, res);









	if (IS_ERR(pcie->msg_base)) {









		return dev_err_probe(dev, PTR_ERR(pcie->msg_base),









				     "unable to ioremap msg resource\n");









	}



















	return 0;









}



















static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie)









{









	struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);









	u32 val;



















	val = readl(pcie->strap_base + STRAP_REG(1));









	val |= LINK_TRAINING_ENABLE;









	writel(val, pcie->strap_base + STRAP_REG(1));



















	return 0;









}



















static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie)









{









	struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);









	u32 val;



















	val = readl(pcie->strap_base + STRAP_REG(1));









	val &= ~LINK_TRAINING_ENABLE;









	writel(val, pcie->strap_base + STRAP_REG(1));









}



















static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie)









{









	u32 val;



















	val = cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG,









				  IP_REG_I_DBG_STS_0);









	return val & LINK_COMPLETE;









}



















static const struct cdns_pcie_ops sky1_pcie_ops = {









	.start_link = sky1_pcie_start_link,









	.stop_link = sky1_pcie_stop_link,









	.link_up = sky1_pcie_link_up,









};



















static int sky1_pcie_probe(struct platform_device *pdev)









{









	struct cdns_plat_pcie_of_data *reg_off;









	struct device *dev = &pdev->dev;









	struct pci_host_bridge *bridge;









	struct cdns_pcie *cdns_pcie;









	struct resource_entry *bus;









	struct cdns_pcie_rc *rc;









	struct sky1_pcie *pcie;









	int ret;



















	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);









	if (!pcie)









		return -ENOMEM;



















	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));









	if (!bridge)









		return -ENOMEM;



















	ret = sky1_pcie_resource_get(pdev, pcie);









	if (ret < 0)









		return ret;



















	bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);









	if (!bus)









		return -ENODEV;



















	pcie->cfg = pci_ecam_create(dev, pcie->cfg_res, bus->res,









				    &pci_generic_ecam_ops);









	if (IS_ERR(pcie->cfg))









		return PTR_ERR(pcie->cfg);



















	bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;









	rc = pci_host_bridge_priv(bridge);









	rc->ecam_supported = 1;









	rc->cfg_base = pcie->cfg->win;









	rc->cfg_res = &pcie->cfg->res;



















	cdns_pcie = &rc->pcie;









	cdns_pcie->dev = dev;









	cdns_pcie->ops = &sky1_pcie_ops;









	cdns_pcie->reg_base = pcie->reg_base;









	cdns_pcie->msg_res = pcie->msg_res;









	cdns_pcie->is_rc = 1;



















	reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);









	if (!reg_off)









		return -ENOMEM;



















	reg_off->ip_reg_bank_offset = SKY1_IP_REG_BANK;









	reg_off->ip_cfg_ctrl_reg_offset = SKY1_IP_CFG_CTRL_REG_BANK;









	reg_off->axi_mstr_common_offset = SKY1_IP_AXI_MASTER_COMMON;









	reg_off->axi_slave_offset = SKY1_AXI_SLAVE;









	reg_off->axi_master_offset = SKY1_AXI_MASTER;









	reg_off->axi_hls_offset = SKY1_AXI_HLS_REGISTERS;









	reg_off->axi_ras_offset = SKY1_AXI_RAS_REGISTERS;









	reg_off->axi_dti_offset = SKY1_DTI_REGISTERS;









	cdns_pcie->cdns_pcie_reg_offsets = reg_off;



















	pcie->cdns_pcie = cdns_pcie;









	pcie->cdns_pcie_rc = rc;









	pcie->cfg_base = rc->cfg_base;









	bridge->sysdata = pcie->cfg;



















	rc->vendor_id = PCI_VENDOR_ID_CIX;









	rc->device_id = PCI_DEVICE_ID_CIX_SKY1;









	rc->no_inbound_map = 1;



















	dev_set_drvdata(dev, pcie);



















	ret = cdns_pcie_hpa_host_setup(rc);









	if (ret < 0) {









		pci_ecam_free(pcie->cfg);









		return ret;









	}



















	return 0;









}



















static const struct of_device_id of_sky1_pcie_match[] = {









	{ .compatible = "cix,sky1-pcie-host", },









	{},









};









MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);



















static void sky1_pcie_remove(struct platform_device *pdev)









{









	struct sky1_pcie *pcie = platform_get_drvdata(pdev);



















	pci_ecam_free(pcie->cfg);









}



















static struct platform_driver sky1_pcie_driver = {









	.probe  = sky1_pcie_probe,









	.remove = sky1_pcie_remove,









	.driver = {









		.name = "sky1-pcie",









		.of_match_table = of_sky1_pcie_match,









		.probe_type = PROBE_PREFER_ASYNCHRONOUS,









	},









};









module_platform_driver(sky1_pcie_driver);



















MODULE_LICENSE("GPL");









MODULE_DESCRIPTION("PCIe controller driver for CIX's sky1 SoCs");









MODULE_AUTHOR("Hans Zhang <hans.zhang@cixtech.com>");