Commit 80b0dd1c authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files
Tariq Toukan says:

====================
mlx5-next updates 2025-07-08

The following pull-request contains common mlx5 updates
for your *net-next* tree.

v2: https://lore.kernel.org/1751574385-24672-1-git-send-email-tariqt@nvidia.com

* 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
  net/mlx5: Check device memory pointer before usage
  net/mlx5: fs, fix RDMA TRANSPORT init cleanup flow
  net/mlx5: Add IFC bits for PCIe Congestion Event object
  net/mlx5: Small refactor for general object capabilities
  net/mlx5: fs, add multiple prios to RDMA TRANSPORT steering domain
====================

Link: https://patch.msgid.link/1752002102-11316-1-git-send-email-tariqt@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 0a49abff 70f238c9
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+1 −1
Original line number Diff line number Diff line
@@ -282,7 +282,7 @@ static struct ib_dm *handle_alloc_dm_memic(struct ib_ucontext *ctx,
	int err;
	u64 address;

	if (!MLX5_CAP_DEV_MEM(dm_db->dev, memic))
	if (!dm_db || !MLX5_CAP_DEV_MEM(dm_db->dev, memic))
		return ERR_PTR(-EOPNOTSUPP);

	dm = kzalloc(sizeof(*dm), GFP_KERNEL);
+36 −8
Original line number Diff line number Diff line
@@ -3245,34 +3245,62 @@ static int
init_rdma_transport_rx_root_ns_one(struct mlx5_flow_steering *steering,
				   int vport_idx)
{
	struct mlx5_flow_root_namespace *root_ns;
	struct fs_prio *prio;
	int ret;
	int i;

	steering->rdma_transport_rx_root_ns[vport_idx] =
		create_root_ns(steering, FS_FT_RDMA_TRANSPORT_RX);
	if (!steering->rdma_transport_rx_root_ns[vport_idx])
		return -ENOMEM;

	/* create 1 prio*/
	prio = fs_create_prio(&steering->rdma_transport_rx_root_ns[vport_idx]->ns,
			      MLX5_RDMA_TRANSPORT_BYPASS_PRIO, 1);
	return PTR_ERR_OR_ZERO(prio);
	root_ns = steering->rdma_transport_rx_root_ns[vport_idx];

	for (i = 0; i < MLX5_RDMA_TRANSPORT_BYPASS_PRIO; i++) {
		prio = fs_create_prio(&root_ns->ns, i, 1);
		if (IS_ERR(prio)) {
			ret = PTR_ERR(prio);
			goto err;
		}
	}
	set_prio_attrs(root_ns);
	return 0;

err:
	cleanup_root_ns(root_ns);
	return ret;
}

static int
init_rdma_transport_tx_root_ns_one(struct mlx5_flow_steering *steering,
				   int vport_idx)
{
	struct mlx5_flow_root_namespace *root_ns;
	struct fs_prio *prio;
	int ret;
	int i;

	steering->rdma_transport_tx_root_ns[vport_idx] =
		create_root_ns(steering, FS_FT_RDMA_TRANSPORT_TX);
	if (!steering->rdma_transport_tx_root_ns[vport_idx])
		return -ENOMEM;

	/* create 1 prio*/
	prio = fs_create_prio(&steering->rdma_transport_tx_root_ns[vport_idx]->ns,
			      MLX5_RDMA_TRANSPORT_BYPASS_PRIO, 1);
	return PTR_ERR_OR_ZERO(prio);
	root_ns = steering->rdma_transport_tx_root_ns[vport_idx];

	for (i = 0; i < MLX5_RDMA_TRANSPORT_BYPASS_PRIO; i++) {
		prio = fs_create_prio(&root_ns->ns, i, 1);
		if (IS_ERR(prio)) {
			ret = PTR_ERR(prio);
			goto err;
		}
	}
	set_prio_attrs(root_ns);
	return 0;

err:
	cleanup_root_ns(root_ns);
	return ret;
}

static int init_rdma_transport_rx_root_ns(struct mlx5_flow_steering *steering)
+2 −2
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)

	dm = kzalloc(sizeof(*dm), GFP_KERNEL);
	if (!dm)
		return ERR_PTR(-ENOMEM);
		return NULL;

	spin_lock_init(&dm->lock);

@@ -96,7 +96,7 @@ struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev)
err_steering:
	kfree(dm);

	return ERR_PTR(-ENOMEM);
	return NULL;
}

void mlx5_dm_cleanup(struct mlx5_core_dev *dev)
+0 −3
Original line number Diff line number Diff line
@@ -1102,9 +1102,6 @@ static int mlx5_init_once(struct mlx5_core_dev *dev)
	}

	dev->dm = mlx5_dm_create(dev);
	if (IS_ERR(dev->dm))
		mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));

	dev->tracer = mlx5_fw_tracer_create(dev);
	dev->hv_vhca = mlx5_hv_vhca_create(dev);
	dev->rsc_dump = mlx5_rsc_dump_create(dev);
+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@

#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)

#define MLX5_RDMA_TRANSPORT_BYPASS_PRIO 0
#define MLX5_RDMA_TRANSPORT_BYPASS_PRIO 16
#define MLX5_FS_MAX_POOL_SIZE BIT(30)

enum mlx5_flow_destination_type {
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