Commit 8114f34d authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qualcomm: qmp-pcie: define several new registers 



Define several registers to be used by PCIe QMP PHYs on v6 platforms.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-5-d883acf170f7@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent f9d35dd3

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h

+3 −0
Original line number Diff line number Diff line
@@ -14,4 +14,7 @@ 
#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x20

#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS		0x94



#define QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2		0x024

#define QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2		0x028



#endif

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 
#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3		0x0cc

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6		0x0d8

#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1		0x0dc

#define QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB		0x168

#define QPHY_V6_PCS_G3S2_PRE_GAIN		0x170

#define QPHY_V6_PCS_RX_SIGDET_LVL		0x188

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L	0x190

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H	0x194

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_

#define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_



#define QSERDES_V6_TX_BIST_MODE_LANENO				0x00

#define QSERDES_V6_TX_CLKBUF_ENABLE				0x08

#define QSERDES_V6_TX_TX_EMP_POST1_LVL				0x0c

#define QSERDES_V6_TX_TX_DRV_LVL				0x14