Commit 81403c8d authored by Fuad Tabba's avatar Fuad Tabba Committed by Marc Zyngier
Browse files

KVM: arm64: Remove fixed_config.h header 



The few remaining items needed in fixed_config.h are better
suited for pkvm.h. Move them there and delete it.

No functional change intended.

Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Link: https://lore.kernel.org/r/20241216105057.579031-11-tabba@google.com


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 3d7ff007

arch/arm64/kvm/hyp/include/nvhe/fixed_config.h

deleted100644 → 0
+0 −206
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2021 Google LLC

 * Author: Fuad Tabba <tabba@google.com>

 */



#ifndef __ARM64_KVM_FIXED_CONFIG_H__

#define __ARM64_KVM_FIXED_CONFIG_H__



#include <asm/sysreg.h>



/*

 * This file contains definitions for features to be allowed or restricted for

 * guest virtual machines, depending on the mode KVM is running in and on the

 * type of guest that is running.

 *

 * Each field in the masks represents the highest supported *unsigned* value for

 * the feature, if supported by the system.

 *

 * If a feature field is not present in either, than it is not supported.

 *

 * The approach taken for protected VMs is to allow features that are:

 * - Needed by common Linux distributions (e.g., floating point)

 * - Trivial to support, e.g., supporting the feature does not introduce or

 * require tracking of additional state in KVM

 * - Cannot be trapped or prevent the guest from using anyway

 */



/*

 * Allow for protected VMs:

 * - Floating-point and Advanced SIMD

 * - Data Independent Timing

 * - Spectre/Meltdown Mitigation

 *

 * Restrict to the following *unsigned* features for protected VMs:

 * - AArch64 guests only (no support for AArch32 guests):

 *	AArch32 adds complexity in trap handling, emulation, condition codes,

 *	etc...

 * - RAS (v1)

 *	Supported by KVM

 */

#define PVM_ID_AA64PFR0_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) | \

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | \

	ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL0, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL1, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL2, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL3, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, IMP) \

	)



/*

 * Allow for protected VMs:

 * - Branch Target Identification

 * - Speculative Store Bypassing

 */

#define PVM_ID_AA64PFR1_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_BT) | \

	ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SSBS) \

	)



#define PVM_ID_AA64PFR2_ALLOW 0ULL



/*

 * Allow for protected VMs:

 * - Mixed-endian

 * - Distinction between Secure and Non-secure Memory

 * - Mixed-endian at EL0 only

 * - Non-context synchronizing exception entry and exit

 *

 * Restrict to the following *unsigned* features for protected VMs:

 * - 40-bit IPA

 * - 16-bit ASID

 */

#define PVM_ID_AA64MMFR0_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \

	)



/*

 * Allow for protected VMs:

 * - Hardware translation table updates to Access flag and Dirty state

 * - Number of VMID bits from CPU

 * - Hierarchical Permission Disables

 * - Privileged Access Never

 * - SError interrupt exceptions from speculative reads

 * - Enhanced Translation Synchronization

 * - Control for cache maintenance permission

 */

#define PVM_ID_AA64MMFR1_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_CMOW) \

	)



/*

 * Allow for protected VMs:

 * - Common not Private translations

 * - User Access Override

 * - IESB bit in the SCTLR_ELx registers

 * - Unaligned single-copy atomicity and atomic functions

 * - ESR_ELx.EC value on an exception by read access to feature ID space

 * - TTL field in address operations.

 * - Break-before-make sequences when changing translation block size

 * - E0PDx mechanism

 */

#define PVM_ID_AA64MMFR2_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CnP) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_UAO) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IESB) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_AT) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IDS) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_TTL) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_BBM) | \

	ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_E0PD) \

	)



#define PVM_ID_AA64MMFR3_ALLOW (0ULL)



/*

 * No support for Scalable Vectors for protected VMs:

 *	Requires additional support from KVM, e.g., context-switching and

 *	trapping at EL2

 */

#define PVM_ID_AA64ZFR0_ALLOW (0ULL)



/*

 * No support for debug, including breakpoints, and watchpoints for protected

 * VMs:

 *	The Arm architecture mandates support for at least the Armv8 debug

 *	architecture, which would include at least 2 hardware breakpoints and

 *	watchpoints. Providing that support to protected guests adds

 *	considerable state and complexity. Therefore, the reserved value of 0 is

 *	used for debug-related fields.

 */

#define PVM_ID_AA64DFR0_ALLOW (0ULL)

#define PVM_ID_AA64DFR1_ALLOW (0ULL)



/*

 * No support for implementation defined features.

 */

#define PVM_ID_AA64AFR0_ALLOW (0ULL)

#define PVM_ID_AA64AFR1_ALLOW (0ULL)



/*

 * No restrictions on instructions implemented in AArch64.

 */

#define PVM_ID_AA64ISAR0_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \

	)



/* Restrict pointer authentication to the basic version. */

#define PVM_ID_AA64ISAR1_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), ID_AA64ISAR1_EL1_APA_PAuth) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), ID_AA64ISAR1_EL1_API_PAuth) \

	)



#define PVM_ID_AA64ISAR2_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_ATS1A)| \

	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3), ID_AA64ISAR2_EL1_APA3_PAuth) \

	)



bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code);

bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code);

void kvm_init_pvm_id_regs(struct kvm_vcpu *vcpu);

int kvm_check_pvm_sysreg_table(void);



#endif /* __ARM64_KVM_FIXED_CONFIG_H__ */

arch/arm64/kvm/hyp/include/nvhe/pkvm.h

+5 −0
Original line number Diff line number Diff line
@@ -72,4 +72,9 @@ struct pkvm_hyp_vcpu *pkvm_load_hyp_vcpu(pkvm_handle_t handle, 
					 unsigned int vcpu_idx);

void pkvm_put_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu);



bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code);

bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code);

void kvm_init_pvm_id_regs(struct kvm_vcpu *vcpu);

int kvm_check_pvm_sysreg_table(void);



#endif /* __ARM64_KVM_NVHE_PKVM_H__ */

arch/arm64/kvm/hyp/nvhe/pkvm.c

+0 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ 


#include <asm/kvm_emulate.h>



#include <nvhe/fixed_config.h>

#include <nvhe/mem_protect.h>

#include <nvhe/memory.h>

#include <nvhe/pkvm.h>

arch/arm64/kvm/hyp/nvhe/setup.c

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ 


#include <nvhe/early_alloc.h>

#include <nvhe/ffa.h>

#include <nvhe/fixed_config.h>

#include <nvhe/gfp.h>

#include <nvhe/memory.h>

#include <nvhe/mem_protect.h>

arch/arm64/kvm/hyp/nvhe/switch.c

+0 −1
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ 
#include <asm/debug-monitors.h>

#include <asm/processor.h>



#include <nvhe/fixed_config.h>

#include <nvhe/mem_protect.h>



/* Non-VHE specific context */