Commit 81508279 authored by David Yat Sin's avatar David Yat Sin Committed by Alex Deucher
Browse files

drm/amdkfd: Preserve cp_hqd_pq_control on update_mqd 



When userspace applications call AMDKFD_IOC_UPDATE_QUEUE. Preserve
bitfields that do not need to be modified as they contain flags to
track queue states that are used by CP FW.

Signed-off-by: default avatarDavid Yat Sin <David.YatSin@amd.com>
Reviewed-by: default avatarJay Cornwall <jay.cornwall@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ee3dc9e2

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c

+4 −2
Original line number Diff line number Diff line
@@ -107,6 +107,8 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, 
	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |

			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;

	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;



	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
@@ -167,10 +169,10 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 


	m = get_mqd(mqd);



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;

	m->cp_hqd_pq_control |=

			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;



	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);



	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c

+3 −2
Original line number Diff line number Diff line
@@ -154,6 +154,8 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, 
	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |

			0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;

	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;



	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
@@ -221,10 +223,9 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 


	m = get_mqd(mqd);



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;

	m->cp_hqd_pq_control |=

			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;

	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);



	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c

+3 −2
Original line number Diff line number Diff line
@@ -121,6 +121,8 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, 
	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |

			0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;

	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;



	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
@@ -184,10 +186,9 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 


	m = get_mqd(mqd);



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;

	m->cp_hqd_pq_control |=

			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;

	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);



	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

+4 −1
Original line number Diff line number Diff line
@@ -183,6 +183,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, 
	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |

			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;



	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;



	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
@@ -245,7 +248,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 


	m = get_mqd(mqd);



	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK;

	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;

	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);