Commit 81791c45 authored by Xiangxu Yin's avatar Xiangxu Yin Committed by Vinod Koul
Browse files

phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support 



Add QCS615-specific configuration for USB/DP PHY, including DP init
routines, voltage swing tables, and platform data. Add compatible
"qcs615-qmp-usb3-dp-phy".

Note: SW_PORTSELECT handling for orientation flip is not implemented
due to QCS615 fixed-orientation design and non-standard lane mapping.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarXiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://patch.msgid.link/20251215-add-displayport-support-for-qcs615-platform-v8-12-cbc72c88a44e@oss.qualcomm.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent c1282d5f

drivers/phy/qualcomm/phy-qcom-qmp-usbc.c

+413 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include "phy-qcom-qmp-pcs-misc-v3.h"



#include "phy-qcom-qmp-dp-phy.h"

#include "phy-qcom-qmp-dp-phy-v2.h"



#define PHY_INIT_COMPLETE_TIMEOUT		10000

#define SW_PORTSELECT_VAL			BIT(0)
@@ -289,6 +290,83 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),

};



static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02),

};



static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_rbr[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c),

	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),

};



static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24),

	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),

};



static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr2[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),

};



static const struct qmp_phy_init_tbl qmp_v2_dp_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRANSCEIVER_BIAS_EN, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_VMODE_CTRL1, 0x40),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_PRE_STALL_LDO_BOOST_EN, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_INTERFACE_SELECT, 0x3d),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_CLKBUF_ENABLE, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_RESET_TSYNC_EN, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRAN_DRVR_EMP_EN, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_INTERFACE_MODE, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_EMP_POST1_LVL, 0x2b),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_DRV_LVL, 0x2f),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_BAND, 0x4),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_TX, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_RX, 0x12),

};



struct qmp_usbc_offsets {

	u16 serdes;

	u16 pcs;
@@ -434,6 +512,10 @@ static const char * const usb3phy_reset_l[] = { 
	"phy_phy", "phy",

};



static const char * const usb3dpphy_reset_l[] = {

	"phy_phy", "dp_phy",

};



static const struct regulator_bulk_data qmp_phy_msm8998_vreg_l[] = {

	{ .supply = "vdda-phy", .init_load_uA = 68600 },

	{ .supply = "vdda-pll", .init_load_uA = 14200 },
@@ -459,6 +541,34 @@ static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 = { 
	.rx2		= 0x800,

};



static const struct qmp_usbc_offsets qmp_usbc_usb3dp_offsets_qcs615 = {

	.serdes		= 0x0,

	.pcs		= 0xc00,

	.pcs_misc	= 0xa00,

	.tx		= 0x200,

	.rx		= 0x400,

	.tx2		= 0x600,

	.rx2		= 0x800,

	.dp_serdes	= 0x1c00,

	.dp_txa		= 0x1400,

	.dp_txb		= 0x1800,

	.dp_dp_phy	= 0x1000,

};



static const u8 qmp_v2_dp_pre_emphasis_hbr2_rbr[4][4] = {

	{0x00, 0x0b, 0x12, 0xff},

	{0x00, 0x0a, 0x12, 0xff},

	{0x00, 0x0c, 0xff, 0xff},

	{0xff, 0xff, 0xff, 0xff}

};



static const u8 qmp_v2_dp_voltage_swing_hbr2_rbr[4][4] = {

	{0x07, 0x0f, 0x14, 0xff},

	{0x11, 0x1d, 0x1f, 0xff},

	{0x18, 0x1f, 0xff, 0xff},

	{0xff, 0xff, 0xff, 0xff}

};



static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {

	.offsets		= &qmp_usbc_offsets_v3_qcm2290,
@@ -531,6 +641,51 @@ static const struct qmp_phy_cfg qcs615_usb3phy_cfg = { 
	.regs			= qmp_v3_usb3phy_regs_layout_qcm2290,

};



static void qmp_v2_dp_aux_init(struct qmp_usbc *qmp);

static void qmp_v2_configure_dp_tx(struct qmp_usbc *qmp);

static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp);

static int qmp_v2_calibrate_dp_phy(struct qmp_usbc *qmp);



static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = {

	.offsets		= &qmp_usbc_usb3dp_offsets_qcs615,



	.serdes_tbl		= qcm2290_usb3_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(qcm2290_usb3_serdes_tbl),

	.tx_tbl			= qcm2290_usb3_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_tx_tbl),

	.rx_tbl			= qcm2290_usb3_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_rx_tbl),

	.pcs_tbl		= qcm2290_usb3_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(qcm2290_usb3_pcs_tbl),



	.regs			= qmp_v3_usb3phy_regs_layout_qcm2290,



	.dp_serdes_tbl		= qmp_v2_dp_serdes_tbl,

	.dp_serdes_tbl_num	= ARRAY_SIZE(qmp_v2_dp_serdes_tbl),

	.dp_tx_tbl		= qmp_v2_dp_tx_tbl,

	.dp_tx_tbl_num		= ARRAY_SIZE(qmp_v2_dp_tx_tbl),



	.serdes_tbl_rbr		= qmp_v2_dp_serdes_tbl_rbr,

	.serdes_tbl_rbr_num	= ARRAY_SIZE(qmp_v2_dp_serdes_tbl_rbr),

	.serdes_tbl_hbr		= qmp_v2_dp_serdes_tbl_hbr,

	.serdes_tbl_hbr_num	= ARRAY_SIZE(qmp_v2_dp_serdes_tbl_hbr),

	.serdes_tbl_hbr2	= qmp_v2_dp_serdes_tbl_hbr2,

	.serdes_tbl_hbr2_num	= ARRAY_SIZE(qmp_v2_dp_serdes_tbl_hbr2),



	.swing_tbl		= &qmp_v2_dp_voltage_swing_hbr2_rbr,

	.pre_emphasis_tbl	= &qmp_v2_dp_pre_emphasis_hbr2_rbr,



	.dp_aux_init		= qmp_v2_dp_aux_init,

	.configure_dp_tx	= qmp_v2_configure_dp_tx,

	.configure_dp_phy	= qmp_v2_configure_dp_phy,

	.calibrate_dp_phy	= qmp_v2_calibrate_dp_phy,



	.reset_list		= usb3dpphy_reset_l,

	.num_resets		= ARRAY_SIZE(usb3dpphy_reset_l),

	.vreg_list		= qmp_phy_qcs615_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_qcs615_vreg_l),

};



static void qmp_usbc_set_phy_mode(struct qmp_usbc *qmp, bool is_dp)

{

	if (qmp->tcsr_map && qmp->dp_phy_mode_reg)
@@ -589,6 +744,253 @@ static int qmp_usbc_com_exit(struct phy *phy) 
	return 0;

}



static void qmp_v2_dp_aux_init(struct qmp_usbc *qmp)

{

	writel(DP_PHY_PD_CTL_AUX_PWRDN |

	       DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |

	       DP_PHY_PD_CTL_PLL_PWRDN,

	       qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);



	writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |

	       DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |

	       DP_PHY_PD_CTL_PLL_PWRDN,

	       qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);



	writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);

	writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);

	writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);

	writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);

	writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);

	writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);

	writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);

	writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);

	writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);

	writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);

	qmp->dp_aux_cfg = 0;



	writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |

	       PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |

	       PHY_AUX_REQ_ERR_MASK,

	       qmp->dp_dp_phy + QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK);

}



static int qmp_v2_configure_dp_swing(struct qmp_usbc *qmp)

{

	const struct qmp_phy_cfg *cfg = qmp->cfg;

	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;

	void __iomem *tx = qmp->dp_tx;

	void __iomem *tx2 = qmp->dp_tx2;

	unsigned int v_level = 0, p_level = 0;

	u8 voltage_swing_cfg, pre_emphasis_cfg;

	int i;



	if (dp_opts->lanes > 4) {

		dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes);

		return -EINVAL;

	}



	for (i = 0; i < dp_opts->lanes; i++) {

		v_level = max(v_level, dp_opts->voltage[i]);

		p_level = max(p_level, dp_opts->pre[i]);

	}



	if (v_level > 4 || p_level > 4) {

		dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n",

			v_level, p_level);

		return -EINVAL;

	}



	voltage_swing_cfg = (*cfg->swing_tbl)[v_level][p_level];

	pre_emphasis_cfg = (*cfg->pre_emphasis_tbl)[v_level][p_level];



	voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;

	pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;



	if (voltage_swing_cfg == 0xff && pre_emphasis_cfg == 0xff)

		return -EINVAL;



	writel(voltage_swing_cfg, tx + QSERDES_V2_TX_TX_DRV_LVL);

	writel(pre_emphasis_cfg, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL);

	writel(voltage_swing_cfg, tx2 + QSERDES_V2_TX_TX_DRV_LVL);

	writel(pre_emphasis_cfg, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL);



	return 0;

}



static void qmp_usbc_configure_dp_mode(struct qmp_usbc *qmp)

{

	bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);

	u32 val;



	val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |

	      DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN;



	writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);



	if (reverse)

		writel(0xc9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);

	else

		writel(0xd9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);

}



static int qmp_usbc_configure_dp_clocks(struct qmp_usbc *qmp)

{

	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;

	u32 phy_vco_div;

	unsigned long pixel_freq;



	switch (dp_opts->link_rate) {

	case 1620:

		phy_vco_div = 0x1;

		pixel_freq = 1620000000UL / 2;

		break;

	case 2700:

		phy_vco_div = 0x1;

		pixel_freq = 2700000000UL / 2;

		break;

	case 5400:

		phy_vco_div = 0x2;

		pixel_freq = 5400000000UL / 4;

		break;

	default:

		dev_err(qmp->dev, "link rate:%d not supported\n", dp_opts->link_rate);

		return -EINVAL;

	}

	writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_VCO_DIV);



	clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);

	clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);



	return 0;

}



static void qmp_v2_configure_dp_tx(struct qmp_usbc *qmp)

{

	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;

	void __iomem *tx = qmp->dp_tx;

	void __iomem *tx2 = qmp->dp_tx2;



	/* program default setting first */

	writel(0x2a, tx + QSERDES_V2_TX_TX_DRV_LVL);

	writel(0x20, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL);

	writel(0x2a, tx2 + QSERDES_V2_TX_TX_DRV_LVL);

	writel(0x20, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL);



	if (dp_opts->link_rate >= 2700) {

		writel(0xc4, tx + QSERDES_V2_TX_LANE_MODE_1);

		writel(0xc4, tx2 + QSERDES_V2_TX_LANE_MODE_1);

	} else {

		writel(0xc6, tx + QSERDES_V2_TX_LANE_MODE_1);

		writel(0xc6, tx2 + QSERDES_V2_TX_LANE_MODE_1);

	}



	qmp_v2_configure_dp_swing(qmp);

}



static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp)

{

	u32 status;

	int ret;



	qmp_usbc_configure_dp_mode(qmp);



	writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL);

	writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL);



	ret = qmp_usbc_configure_dp_clocks(qmp);

	if (ret)

		return ret;



	writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);

	writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);

	writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);

	writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);



	writel(0x20, qmp->dp_serdes + QSERDES_COM_RESETSM_CNTRL);



	if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_C_READY_STATUS,

			       status,

			       ((status & BIT(0)) > 0),

			       500,

			       10000)) {

		dev_err(qmp->dev, "C_READY not ready\n");

		return -ETIMEDOUT;

	}



	if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS,

			       status,

			       ((status & BIT(0)) > 0),

			       500,

			       10000)){

		dev_err(qmp->dev, "FREQ_DONE not ready\n");

		return -ETIMEDOUT;

	}



	if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS,

			       status,

			       ((status & BIT(1)) > 0),

			       500,

			       10000)){

		dev_err(qmp->dev, "PLL_LOCKED not ready\n");

		return -ETIMEDOUT;

	}



	writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);



	if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS,

			       status,

			       ((status & BIT(0)) > 0),

			       500,

			       10000)){

		dev_err(qmp->dev, "TSYNC_DONE not ready\n");

		return -ETIMEDOUT;

	}



	if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS,

			       status,

			       ((status & BIT(1)) > 0),

			       500,

			       10000)){

		dev_err(qmp->dev, "PHY_READY not ready\n");

		return -ETIMEDOUT;

	}



	writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN);

	writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN);

	writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV);

	writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN);

	writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN);

	writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV);



	writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);

	writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);



	if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS,

			       status,

			       ((status & BIT(1)) > 0),

			       500,

			       10000)){

		dev_err(qmp->dev, "PHY_READY not ready\n");

		return -ETIMEDOUT;

	}



	return 0;

}



static int qmp_v2_calibrate_dp_phy(struct qmp_usbc *qmp)

{

	static const u8 cfg1_settings[] = {0x13, 0x23, 0x1d};

	u8 val;



	qmp->dp_aux_cfg++;

	qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);

	val = cfg1_settings[qmp->dp_aux_cfg];



	writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);



	return 0;

}



static int qmp_usbc_usb_power_on(struct phy *phy)

{

	struct qmp_usbc *qmp = phy_get_drvdata(phy);
@@ -855,6 +1257,14 @@ static int qmp_usbc_dp_power_on(struct phy *phy) 
	void __iomem *tx = qmp->dp_tx;

	void __iomem *tx2 = qmp->dp_tx2;



	/*

	 * FIXME: SW_PORTSELECT handling for DP orientation flip is not implemented.

	 * Expected:

	 * - For standard lane mapping: configure SW_PORTSELECT in QSERDES_DP_PHY_CFG_1.

	 * - For non-standard mapping: pass orientation to dp_ctrl and handle flip

	 *   via logical2physical lane remapping.

	 */



	mutex_lock(&qmp->phy_mutex);



	qmp_usbc_dp_serdes_init(qmp);
@@ -1600,6 +2010,9 @@ static const struct of_device_id qmp_usbc_of_match_table[] = { 
	}, {

		.compatible = "qcom,qcm2290-qmp-usb3-phy",

		.data = &qcm2290_usb3phy_cfg,

	}, {

		.compatible = "qcom,qcs615-qmp-usb3-dp-phy",

		.data =  &qcs615_usb3dp_phy_cfg,

	}, {

		.compatible = "qcom,qcs615-qmp-usb3-phy",

		.data = &qcs615_usb3phy_cfg,