Commit 8185461e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2026-02-06' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "The usual xe/amdgpu selection, and a couple of misc changes for
  gma500, mgag200 and bridge. There is a nouveau revert, and also a set
  of changes that fix a regression since we moved to 570 firmware.
  Suspend/resume was broken on a bunch of GPUs. The fix looks big, but
  it's mostly just refactoring to pass an extra bit down the nouveau
  abstractions to the firmware command.

  amdgpu:
   - MES 11 old firmware compatibility fix
   - ASPM fix
   - DC LUT fixes

  amdkfd:
   - Fix possible double deletion of validate list

  xe:
   - Fix topology query pointer advance
   - A couple of kerneldoc fixes
   - Disable D3Cold for BMG only on specific platforms
   - Fix CFI violation in debugfs access

  nouveau:
   - Revert adding atomic commit functions as it regresses pre-nv50
   - Fix suspend/resume bugs exposed by enabling 570 firmware

  gma500:
   - Revert a regression caused by vblank changes

  mgag200:
   - Replace a busy loop with a polling loop to fix that blocking 1 cpu
     for 300 ms roughly every 20 minutes

bridge:
   - imx8mp-hdmi-pa: Use runtime pm to fix a bug in channel ordering"

* tag 'drm-fixes-2026-02-06' of https://gitlab.freedesktop.org/drm/kernel:
  drm/xe/guc: Fix CFI violation in debugfs access.
  drm/bridge: imx8mp-hdmi-pai: enable PM runtime
  drm/xe/pm: Disable D3Cold for BMG only on specific platforms
  drm/xe: Fix kerneldoc for xe_tlb_inval_job_alloc_dep
  drm/xe: Fix kerneldoc for xe_gt_tlb_inval_init_early
  drm/xe: Fix kerneldoc for xe_migrate_exec_queue
  drm/xe/query: Fix topology query pointer advance
  drm/mgag200: fix mgag200_bmc_stop_scanout()
  nouveau/gsp: fix suspend/resume regression on r570 firmware
  nouveau: add a third state to the fini handler.
  nouveau/gsp: use rpc sequence numbers properly.
  drm/amdgpu: Fix double deletion of validate_list
  drm/amd/display: remove assert around dpp_base replacement
  drm/amd/display: extend delta clamping logic to CM3 LUT helper
  drm/amd/display: fix wrong color value mapping on MCM shaper LUT
  Revert "drm/amd: Check if ASPM is enabled from PCIe subsystem"
  drm/amd: Set minimum version for set_hw_resource_1 on gfx11 to 0x52
  Revert "drm/gma500: use drm_crtc_vblank_crtc()"
  Revert "drm/nouveau/disp: Set drm_mode_config_funcs.atomic_(check|commit)"
parents 06bc4e26 7ef92d2e

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+7 −7
Original line number Diff line number Diff line
@@ -1920,21 +1920,21 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 


	/* Make sure restore workers don't access the BO any more */

	mutex_lock(&process_info->lock);

	list_del(&mem->validate_list);

	if (!list_empty(&mem->validate_list))

		list_del_init(&mem->validate_list);

	mutex_unlock(&process_info->lock);



	ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);

	if (unlikely(ret))

		return ret;



	/* Cleanup user pages and MMU notifiers */

	if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {

		amdgpu_hmm_unregister(mem->bo);

		mutex_lock(&process_info->notifier_lock);

		amdgpu_hmm_range_free(mem->range);

		mutex_unlock(&process_info->notifier_lock);

		mem->range = NULL;

	}



	ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);

	if (unlikely(ret))

		return ret;



	amdgpu_amdkfd_remove_eviction_fence(mem->bo,

					process_info->eviction_fence);

	pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+0 −3
Original line number Diff line number Diff line
@@ -2405,9 +2405,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, 
			return -ENODEV;

	}



	if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))

		amdgpu_aspm = 0;



	if (amdgpu_virtual_display ||

	    amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK))

		supports_atomic = true;

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+1 −1
Original line number Diff line number Diff line
@@ -1671,7 +1671,7 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 
	if (r)

		goto failure;



	if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) {

	if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) {

		r = mes_v11_0_set_hw_resources_1(&adev->mes);

		if (r) {

			DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

+29 −8
Original line number Diff line number Diff line
@@ -105,7 +105,10 @@ void cm_helper_program_gamcor_xfer_func( 
#define NUMBER_REGIONS     32

#define NUMBER_SW_SEGMENTS 16



bool cm3_helper_translate_curve_to_hw_format(

#define DC_LOGGER \

		ctx->logger



bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx,

					     const struct dc_transfer_func *output_tf,

					     struct pwl_params *lut_params, bool fixpoint)

{
@@ -163,6 +166,11 @@ bool cm3_helper_translate_curve_to_hw_format( 
			hw_points += (1 << seg_distr[k]);

	}



	// DCN3+ have 257 pts in lieu of no separate slope registers

	// Prior HW had 256 base+slope pairs

	// Shaper LUT (i.e. fixpoint == true) is still 256 bases and 256 deltas

	hw_points = fixpoint ? (hw_points - 1) : hw_points;



	j = 0;

	for (k = 0; k < (region_end - region_start); k++) {

		increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
@@ -223,8 +231,6 @@ bool cm3_helper_translate_curve_to_hw_format( 
	corner_points[1].green.slope = dc_fixpt_zero;

	corner_points[1].blue.slope = dc_fixpt_zero;



	// DCN3+ have 257 pts in lieu of no separate slope registers

	// Prior HW had 256 base+slope pairs

	lut_params->hw_points_num = hw_points + 1;



	k = 0;
@@ -248,6 +254,10 @@ bool cm3_helper_translate_curve_to_hw_format( 
	if (fixpoint == true) {

		i = 1;

		while (i != hw_points + 2) {

			uint32_t red_clamp;

			uint32_t green_clamp;

			uint32_t blue_clamp;



			if (i >= hw_points) {

				if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))

					rgb_plus_1->red = dc_fixpt_add(rgb->red,
@@ -260,9 +270,20 @@ bool cm3_helper_translate_curve_to_hw_format( 
							rgb_minus_1->delta_blue);

			}



			rgb->delta_red_reg   = dc_fixpt_clamp_u0d10(rgb->delta_red);

			rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green);

			rgb->delta_blue_reg  = dc_fixpt_clamp_u0d10(rgb->delta_blue);

			rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);

			rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);

			rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);



			red_clamp = dc_fixpt_clamp_u0d14(rgb->delta_red);

			green_clamp = dc_fixpt_clamp_u0d14(rgb->delta_green);

			blue_clamp = dc_fixpt_clamp_u0d14(rgb->delta_blue);



			if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp >> 10)

				DC_LOG_ERROR("Losing delta precision while programming shaper LUT.");



			rgb->delta_red_reg   = red_clamp & 0x3ff;

			rgb->delta_green_reg = green_clamp & 0x3ff;

			rgb->delta_blue_reg  = blue_clamp & 0x3ff;

			rgb->red_reg         = dc_fixpt_clamp_u0d14(rgb->red);

			rgb->green_reg       = dc_fixpt_clamp_u0d14(rgb->green);

			rgb->blue_reg        = dc_fixpt_clamp_u0d14(rgb->blue);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ void cm_helper_program_gamcor_xfer_func( 
	const struct pwl_params *params,

	const struct dcn3_xfer_func_reg *reg);



bool cm3_helper_translate_curve_to_hw_format(

bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx,

	const struct dc_transfer_func *output_tf,

	struct pwl_params *lut_params, bool fixpoint);