Commit 81b3be6c authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/qcom' 

- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM
  implementation (Mayank Rana)

- Rename gen_pci_init() to pci_host_common_ecam_create() and export for use
  by controller drivers (Mayank Rana)

- Add DT binding and driver support for SA8255p, which supports ECAM for
  Configuration Space access (Mayank Rana)

- Update DT binding and driver to describe PHYs and per-Root Port resets in
  a Root Port stanza and deprecate describing them in the host bridge; this
  makes it possible to support multiple Root Ports in the future (Krishna
  Chaitanya Chundru)

* pci/controller/qcom:
  PCI: qcom: Add support for parsing the new Root Port binding
  dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
  PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex
  dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
  PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers
  PCI: dwc: Export DWC MSI controller related APIs
parents d5b0b60a a2fbecdb

Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml

+30 −2
Original line number Diff line number Diff line
@@ -51,10 +51,18 @@ properties: 


  phys:

    maxItems: 1

    deprecated: true

    description:

      This property is deprecated, instead of referencing this property from

      the host bridge node, use the property from the PCIe root port node.



  phy-names:

    items:

      - const: pciephy

    deprecated: true

    description:

      Phandle to the register map node. This property is deprecated, and not

      required to add in the root port also, as the root port has only one phy.



  power-domains:

    maxItems: 1
@@ -71,12 +79,18 @@ properties: 
    maxItems: 12



  perst-gpios:

    description: GPIO controlled connection to PERST# signal

    description: GPIO controlled connection to PERST# signal. This property is

      deprecated, instead of referencing this property from the host bridge node,

      use the reset-gpios property from the root port node.

    maxItems: 1

    deprecated: true



  wake-gpios:

    description: GPIO controlled connection to WAKE# signal

    description: GPIO controlled connection to WAKE# signal. This property is

      deprecated, instead of referencing this property from the host bridge node,

      use the property from the PCIe root port node.

    maxItems: 1

    deprecated: true



  vddpe-3v3-supply:

    description: PCIe endpoint power supply
@@ -85,6 +99,20 @@ properties: 
  opp-table:

    type: object



patternProperties:

  "^pcie@":

    type: object

    $ref: /schemas/pci/pci-pci-bridge.yaml#



    properties:

      reg:

        maxItems: 1



      phys:

        maxItems: 1



    unevaluatedProperties: false



required:

  - reg

  - reg-names

Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml

0 → 100644
+122 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description:

  Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys

  DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode.



properties:

  compatible:

    const: qcom,pcie-sa8255p



  reg:

    description:

      The base address and size of the ECAM area for accessing PCI

      Configuration Space, as accessed from the parent bus. The base

      address corresponds to the first bus in the "bus-range" property. If

      no "bus-range" is specified, this will be bus 0 (the default).

    maxItems: 1



  ranges:

    description:

      As described in IEEE Std 1275-1994, but must provide at least a

      definition of non-prefetchable memory. One or both of prefetchable Memory

      may also be provided.

    minItems: 1

    maxItems: 2



  interrupts:

    minItems: 8

    maxItems: 8



  interrupt-names:

    items:

      - const: msi0

      - const: msi1

      - const: msi2

      - const: msi3

      - const: msi4

      - const: msi5

      - const: msi6

      - const: msi7



  power-domains:

    maxItems: 1



  dma-coherent: true

  iommu-map: true



required:

  - compatible

  - reg

  - ranges

  - power-domains

  - interrupts

  - interrupt-names



allOf:

  - $ref: /schemas/pci/pci-host-bridge.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pci@1c00000 {

           compatible = "qcom,pcie-sa8255p";

           reg = <0x4 0x00000000 0 0x10000000>;

           device_type = "pci";

           #address-cells = <3>;

           #size-cells = <2>;

           ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,

                    <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;

           bus-range = <0x00 0xff>;

           dma-coherent;

           linux,pci-domain = <0>;

           power-domains = <&scmi5_pd 0>;

           iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,

                       <0x100 &pcie_smmu 0x0001 0x1>;

           interrupt-parent = <&intc>;

           interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,

                        <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,

                        <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,

                        <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,

                        <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,

                        <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,

                        <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,

                        <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;

           interrupt-names = "msi0", "msi1", "msi2", "msi3",

                                  "msi4", "msi5", "msi6", "msi7";



           #interrupt-cells = <1>;

           interrupt-map-mask = <0 0 0 0x7>;

           interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

                           <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

                           <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

                           <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;



           pcie@0 {

                   device_type = "pci";

                   reg = <0x0 0x0 0x0 0x0 0x0>;

                   bus-range = <0x01 0xff>;



                   #address-cells = <3>;

                   #size-cells = <2>;

                   ranges;

            };

        };

    };

Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml

+12 −4
Original line number Diff line number Diff line
@@ -165,9 +165,6 @@ examples: 
            iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,

                        <0x100 &apps_smmu 0x1c81 0x1>;



            phys = <&pcie1_phy>;

            phy-names = "pciephy";



            pinctrl-names = "default";

            pinctrl-0 = <&pcie1_clkreq_n>;
@@ -176,7 +173,18 @@ examples: 
            resets = <&gcc GCC_PCIE_1_BCR>;

            reset-names = "pci";



            perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;

            vddpe-3v3-supply = <&pp3300_ssd>;

            pcie1_port0: pcie@0 {

                device_type = "pci";

                reg = <0x0 0x0 0x0 0x0 0x0>;

                bus-range = <0x01 0xff>;



                #address-cells = <3>;

                #size-cells = <2>;

                ranges;

                phys = <&pcie1_phy>;



                reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;

            };

        };

    };

drivers/pci/controller/dwc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ config PCIE_QCOM 
	select PCIE_DW_HOST

	select CRC8

	select PCIE_QCOM_COMMON

	select PCI_HOST_COMMON

	help

	  Say Y here to enable PCIe controller support on Qualcomm SoCs. The

	  PCIe controller uses the DesignWare core plus Qualcomm-specific

drivers/pci/controller/dwc/pcie-designware-host.c

+20 −18
Original line number Diff line number Diff line
@@ -230,7 +230,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) 
	return 0;

}



static void dw_pcie_free_msi(struct dw_pcie_rp *pp)

void dw_pcie_free_msi(struct dw_pcie_rp *pp)

{

	u32 ctrl;
@@ -242,19 +242,34 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp) 


	irq_domain_remove(pp->irq_domain);

}

EXPORT_SYMBOL_GPL(dw_pcie_free_msi);



static void dw_pcie_msi_init(struct dw_pcie_rp *pp)

void dw_pcie_msi_init(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	u64 msi_target = (u64)pp->msi_data;

	u32 ctrl, num_ctrls;



	if (!pci_msi_enabled() || !pp->has_msi_ctrl)

		return;



	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;



	/* Initialize IRQ Status array */

	for (ctrl = 0; ctrl < num_ctrls; ctrl++) {

		dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +

				    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),

				    pp->irq_mask[ctrl]);

		dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +

				    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),

				    ~0);

	}



	/* Program the msi_data */

	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));

	dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));

}

EXPORT_SYMBOL_GPL(dw_pcie_msi_init);



static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)

{
@@ -296,7 +311,7 @@ static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) 
	return 0;

}



static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)

int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct device *dev = pci->dev;
@@ -370,6 +385,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) 


	return 0;

}

EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init);



static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)

{
@@ -888,7 +904,7 @@ static void dw_pcie_config_presets(struct dw_pcie_rp *pp) 
int dw_pcie_setup_rc(struct dw_pcie_rp *pp)

{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	u32 val, ctrl, num_ctrls;

	u32 val;

	int ret;



	/*
@@ -899,20 +915,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) 


	dw_pcie_setup(pci);



	if (pp->has_msi_ctrl) {

		num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;



		/* Initialize IRQ Status array */

		for (ctrl = 0; ctrl < num_ctrls; ctrl++) {

			dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +

					    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),

					    pp->irq_mask[ctrl]);

			dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +

					    (ctrl * MSI_REG_CTRL_BLOCK_SIZE),

					    ~0);

		}

	}



	dw_pcie_msi_init(pp);



	/* Setup RC BARs */