Commit 8236820f authored by Sebastian Brzezinka's avatar Sebastian Brzezinka Committed by Tvrtko Ursulin
Browse files

drm/i915/gt: Relocate compression repacking WA for JSL/EHL 



CACHE_MODE_0 registers should be saved and restored as part of
the context, not during engine reset. Move the related workaround
(Disable Repacking for Compression) from rcs_engine_wa_init()
to icl_ctx_workarounds_init() for Jasper Lake and Elkhart
Lake platforms. This ensures the WA is applied during context
initialisation.

BSPEC: 11322

Fixes: 0ddae025 ("drm/i915: Disable compression tricks on JSL")
Closes: Fixes: 0ddae025 ("drm/i915: Disable compression tricks on JSL")
Signed-off-by: default avatarSebastian Brzezinka <sebastian.brzezinka@intel.com>
Cc: stable@vger.kernel.org # v6.13+
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: default avatarKrzysztof Karas <krzysztof.karas@intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://lore.kernel.org/r/4feaa24094e019e000ceb6011d8cd419b0361b3f.1754902406.git.sebastian.brzezinka@intel.com


(cherry picked from commit c9932f0d)
Signed-off-by: default avatarTvrtko Ursulin <tursulin@ursulin.net>
parent ff646d03

drivers/gpu/drm/i915/gt/intel_workarounds.c

+11 −9
Original line number Diff line number Diff line
@@ -634,6 +634,8 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 
static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,

				     struct i915_wa_list *wal)

{

	struct drm_i915_private *i915 = engine->i915;



	/* Wa_1406697149 (WaDisableBankHangMode:icl) */

	wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
@@ -669,6 +671,15 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 


	/* Wa_1406306137:icl,ehl */

	wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);



	if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {

		/*

		 * Disable Repacking for Compression (masked R/W access)

		 * before rendering compressed surfaces for display.

		 */

		wa_masked_en(wal, CACHE_MODE_0_GEN7,

			     DISABLE_REPACKING_FOR_COMPRESSION);

	}

}



/*
@@ -2306,15 +2317,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);

	}



	if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {

		/*

		 * "Disable Repacking for Compression (masked R/W access)

		 *  before rendering compressed surfaces for display."

		 */

		wa_masked_en(wal, CACHE_MODE_0_GEN7,

			     DISABLE_REPACKING_FOR_COMPRESSION);

	}



	if (GRAPHICS_VER(i915) == 11) {

		/* This is not an Wa. Enable for better image quality */

		wa_masked_en(wal,