Commit 82582f85 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
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iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported 

According to the AMD IOMMU spec, IOMMU hardware reads the entire DTE
in a single 256-bit transaction. It is recommended to update DTE using
128-bit operation followed by an INVALIDATE_DEVTAB_ENTYRY command when
the IV=1b or V=1b before the change.

According to the AMD BIOS and Kernel Developer's Guide (BDKG) dated back
to family 10h Processor [1], which is the first introduction of AMD IOMMU,
AMD processor always has CPUID Fn0000_0001_ECX[CMPXCHG16B]=1.
Therefore, it is safe to assume cmpxchg128 is available with all AMD
processor w/ IOMMU.

In addition, the CMPXCHG16B feature has already been checked separately
before enabling the GA, XT, and GAM modes. Consolidate the detection logic,
and fail the IOMMU initialization if the feature is not supported.

[1] https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/programmer-references/31116.pdf



Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Suggested-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20241118054937.5203-3-suravee.suthikulpanit@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent f20a6e3e

drivers/iommu/amd/init.c

+9 −14
Original line number Diff line number Diff line
@@ -1752,13 +1752,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 
		else

			iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;



		/*

		 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.

		 * GAM also requires GA mode. Therefore, we need to

		 * check cmpxchg16b support before enabling it.

		 */

		if (!boot_cpu_has(X86_FEATURE_CX16) ||

		    ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))

		/* GAM requires GA mode. */

		if ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)

			amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;

		break;

	case 0x11:
@@ -1768,13 +1763,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 
		else

			iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;



		/*

		 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.

		 * XT, GAM also requires GA mode. Therefore, we need to

		 * check cmpxchg16b support before enabling them.

		 */

		if (!boot_cpu_has(X86_FEATURE_CX16) ||

		    ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) {

		/* XT and GAM require GA mode. */

		if ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0) {

			amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;

			break;

		}
@@ -3028,6 +3018,11 @@ static int __init early_amd_iommu_init(void) 
		return -EINVAL;

	}



	if (!boot_cpu_has(X86_FEATURE_CX16)) {

		pr_err("Failed to initialize. The CMPXCHG16B feature is required.\n");

		return -EINVAL;

	}



	/*

	 * Validate checksum here so we don't need to do it when

	 * we actually parse the table