Commit 825aed03 authored by Jan Maslak's avatar Jan Maslak Committed by Matthew Brost
Browse files

drm/xe: Restore engine registers before restarting schedulers after GT reset 



During GT reset recovery in do_gt_restart(), xe_uc_start() was called
before xe_reg_sr_apply_mmio() restored engine-specific registers. This
created a race window where the scheduler could run jobs before hardware
state was fully restored.

This caused failures in eudebug tests (xe_exec_sip_eudebug@breakpoint-
waitsip-*) where TD_CTL register (containing TD_CTL_GLOBAL_DEBUG_ENABLE)
wasn't restored before jobs started executing. Breakpoints would fail to
trigger SIP entry because the debug enable bit wasn't set yet.

Fix by moving xe_uc_start() after all MMIO register restoration,
including engine registers and CCS mode configuration, ensuring all
hardware state is fully restored before any jobs can be scheduled.

Fixes: dd08ebf6 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: default avatarJan Maslak <jan.maslak@intel.com>
Reviewed-by: default avatarJonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251210145618.169625-2-jan.maslak@intel.com
parent d69d3636

drivers/gpu/drm/xe/xe_gt.c

+4 −3
Original line number Diff line number Diff line
@@ -771,9 +771,6 @@ static int do_gt_restart(struct xe_gt *gt) 
		xe_gt_sriov_pf_init_hw(gt);



	xe_mocs_init(gt);

	err = xe_uc_start(&gt->uc);

	if (err)

		return err;



	for_each_hw_engine(hwe, gt, id)

		xe_reg_sr_apply_mmio(&hwe->reg_sr, gt);
@@ -781,6 +778,10 @@ static int do_gt_restart(struct xe_gt *gt) 
	/* Get CCS mode in sync between sw/hw */

	xe_gt_apply_ccs_mode(gt);



	err = xe_uc_start(&gt->uc);

	if (err)

		return err;



	/* Restore GT freq to expected values */

	xe_gt_sanitize_freq(gt);