Commit 82cf3b8a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.12' of... 

Merge tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Add camera, display and GPU clock drivers for Qualcomm SM4450
 - Add a camera clock driver for Qualcomm SM8150
 - Mark a bunch of struct freq_tbl const to reduce .data usage
 - Add Qualcomm MSM8226 A7PLL and Regera PLL support
 - Fix the Qualcomm Lucid 5LPE PLL configuration sequence to not reuse
   Trion, as they do differ
 - A number of fixes to the Qualcomm SM8550 display clock driver
 - Fold Qualcomm SM8650 display clock driver into SM8550 one
 - Add missing clocks and GDSCs needed for audio on Qualcomm MSM8998
 - Add missing USB MP resets, GPLL9, and QUPv3 DFS to Qualcomm SC8180X
 - Fix sdcc clk frequency tables on Qualcomm SC8180X
 - Drop the Qualcomm SM8150 gcc_cpuss_ahb_clk_src
 - Mark Qualcomm PCIe GDSCs as RET_ON on sm8250 and sm8540 to avoid them
   turning off during suspend
 - Use the HW_CTRL mechanism on Qualcomm SM8550 video clock controller
   GDSCs

* tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (47 commits)
  clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's
  clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL
  clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks
  clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks
  clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src
  dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details
  dt-bindings: interconnect: Add Qualcomm IPQ5332 support
  clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks
  dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions
  clk: qcom: Fix SM_CAMCC_8150 dependencies
  clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src
  clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table
  clk: qcom: gcc-sc8180x: Add GPLL9 support
  dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x
  clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x
  clk: qcom: clk-rpmh: Fix overflow in BCM vote
  dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc
  dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc
  dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema
  dt-bindings: clock: Add x1e80100 LPASSCC reset controller
  ...
parents 8400291e d628455a

Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

+4 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
      - qcom,ipq6018-a53pll

      - qcom,ipq8074-a53pll

      - qcom,ipq9574-a73pll

      - qcom,msm8226-a7pll

      - qcom,msm8916-a53pll

      - qcom,msm8939-a53pll
@@ -40,6 +41,9 @@ properties: 


  operating-points-v2: true



  opp-table:

    type: object



required:

  - compatible

  - reg

Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ properties: 
      - description: USB PCIE wrapper pipe clock source



  '#power-domain-cells': false

  '#interconnect-cells':

    const: 1



required:

  - compatible

Documentation/devicetree/bindings/clock/qcom,qcs404-turingcc.yaml

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+47 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,qcs404-turingcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Turing Clock & Reset Controller on QCS404



maintainers:

  - Bjorn Andersson <andersson@kernel.org>



properties:

  compatible:

    const: qcom,qcs404-turingcc



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-qcs404.h>

    clock-controller@800000 {

        compatible = "qcom,qcs404-turingcc";

        reg = <0x00800000 0x30000>;

        clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;



        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml

+10 −3
Original line number Diff line number Diff line
@@ -18,9 +18,16 @@ description: | 


properties:

  compatible:

    enum:

    oneOf:

      - enum:

          - qcom,sc8280xp-lpassaudiocc

          - qcom,sc8280xp-lpasscc

      - items:

          - const: qcom,x1e80100-lpassaudiocc

          - const: qcom,sc8280xp-lpassaudiocc

      - items:

          - const: qcom,x1e80100-lpasscc

          - const: qcom,sc8280xp-lpasscc



  reg:

    maxItems: 1

Documentation/devicetree/bindings/clock/qcom,sm4450-camcc.yaml

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+63 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm4450-camcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Camera Clock & Reset Controller on SM4450



maintainers:

  - Ajit Pandey <quic_ajipan@quicinc.com>

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm camera clock control module provides the clocks, resets and power

  domains on SM4450



  See also:: include/dt-bindings/clock/qcom,sm4450-camcc.h



properties:

  compatible:

    const: qcom,sm4450-camcc



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Board XO source

      - description: Camera AHB clock source from GCC



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/clock/qcom,sm4450-gcc.h>

    clock-controller@ade0000 {

      compatible = "qcom,sm4450-camcc";

      reg = <0x0ade0000 0x20000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&gcc GCC_CAMERA_AHB_CLK>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...