Commit 82dad698 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of https://github.com/openrisc/linux 

Pull OpenRISC updates from Stafford Horne:
 "Just a few documentation updates from the community:

   - Device tree documentation conversion from txt to yaml

   - Documentation addition to help users getting started with initramfs
     on OpenRISC

* tag 'for-linus' of https://github.com/openrisc/linux:
  dt-bindings: interrupt-controller: Convert openrisc,ompic to DT schema
  dt-bindings: interrupt-controller: Convert opencores,or1k-pic to DT schema
  Documentation:openrisc: Add build instructions with initramfs
parents f563ba4a f698ee1f

Documentation/arch/openrisc/openrisc_port.rst

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@@ -40,6 +40,12 @@ Build the Linux kernel as usual:: 
	make ARCH=openrisc CROSS_COMPILE="or1k-linux-" defconfig

	make ARCH=openrisc CROSS_COMPILE="or1k-linux-"



If you want to embed initramfs in the kernel, also pass ``CONFIG_INITRAMFS_SOURCE``. For example::



	make ARCH=openrisc CROSS_COMPILE="or1k-linux-" CONFIG_INITRAMFS_SOURCE="path/to/rootfs path/to/devnodes"



For more information on this, please check Documentation/filesystems/ramfs-rootfs-initramfs.rst.



3) Running on FPGA (optional)



The OpenRISC community typically uses FuseSoC to manage building and programming

Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.txt

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OpenRISC 1000 Programmable Interrupt Controller



Required properties:



- compatible : should be "opencores,or1k-pic-level" for variants with

  level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with

  edge triggered interrupt lines or "opencores,or1200-pic" for machines

  with the non-spec compliant or1200 type implementation.



  "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",

  but this is only for backwards compatibility.



- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.



Example:



intc: interrupt-controller {

	compatible = "opencores,or1k-pic-level";

	interrupt-controller;

	#interrupt-cells = <1>;

};

Documentation/devicetree/bindings/interrupt-controller/opencores,or1k-pic.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/opencores,or1k-pic.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: OpenRISC 1000 Programmable Interrupt Controller



maintainers:

  - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>



properties:

  compatible:

    enum:

      - opencores,or1k-pic-level

      - opencores,or1k-pic-edge

      - opencores,or1200-pic

      - opencores,or1k-pic



  interrupt-controller: true



  '#interrupt-cells':

    const: 1



required:

  - compatible

  - interrupt-controller

  - '#interrupt-cells'



additionalProperties: false



examples:

  - |

    interrupt-controller {

        compatible = "opencores,or1k-pic-level";

        interrupt-controller;

        #interrupt-cells = <1>;

    };

Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt

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Open Multi-Processor Interrupt Controller



Required properties:



- compatible : This should be "openrisc,ompic"

- reg : Specifies base physical address and size of the register space. The

  size is based on the number of cores the controller has been configured

  to handle, this should be set to 8 bytes per cpu core.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : This should be set to 0 as this will not be an irq

  parent.

- interrupts : Specifies the interrupt line to which the ompic is wired.



Example:



ompic: interrupt-controller@98000000 {

	compatible = "openrisc,ompic";

	reg = <0x98000000 16>;

	interrupt-controller;

	#interrupt-cells = <0>;

	interrupts = <1>;

};

Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/openrisc,ompic.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Open Multi-Processor Interrupt Controller



maintainers:

  - Stafford Horne <shorne@gmail.com>



properties:

  compatible:

    items:

      - const: openrisc,ompic



  reg:

    maxItems: 1



  interrupt-controller: true



  '#interrupt-cells':

    const: 0



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupt-controller

  - '#interrupt-cells'

  - interrupts



additionalProperties: false



examples:

  - |

    interrupt-controller@98000000 {

        compatible = "openrisc,ompic";

        reg = <0x98000000 16>;

        interrupt-controller;

        #interrupt-cells = <0>;

        interrupts = <1>;

    };