Commit 8300438d authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Georgi Djakov
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dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC 



Document the RPMh Network-On-Chip Interconnect of the Eliza platform.

Signed-off-by: default avatarOdelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://msgid.link/20260224-eliza-interconnect-v4-1-ad75855d5018@oss.qualcomm.com


Signed-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parent ae66be59

Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/interconnect/qcom,eliza-rpmh.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm RPMh Network-On-Chip Interconnect on Eliza SoC



maintainers:

  - Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>



description: |

  RPMh interconnect providers support system bandwidth requirements through

  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is

  able to communicate with the BCM through the Resource State Coordinator (RSC)

  associated with each execution environment. Provider nodes must point to at

  least one RPMh device child node pertaining to their RSC and each provider

  can map to multiple RPMh resources.



  See also: include/dt-bindings/interconnect/qcom,eliza-rpmh.h



properties:

  compatible:

    enum:

      - qcom,eliza-aggre1-noc

      - qcom,eliza-aggre2-noc

      - qcom,eliza-clk-virt

      - qcom,eliza-cnoc-cfg

      - qcom,eliza-cnoc-main

      - qcom,eliza-gem-noc

      - qcom,eliza-lpass-ag-noc

      - qcom,eliza-lpass-lpiaon-noc

      - qcom,eliza-lpass-lpicx-noc

      - qcom,eliza-mc-virt

      - qcom,eliza-mmss-noc

      - qcom,eliza-nsp-noc

      - qcom,eliza-pcie-anoc

      - qcom,eliza-system-noc



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



required:

  - compatible



allOf:

  - $ref: qcom,rpmh-common.yaml#

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,eliza-clk-virt

              - qcom,eliza-mc-virt

    then:

      properties:

        reg: false

    else:

      required:

        - reg



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,eliza-aggre1-noc

    then:

      properties:

        clocks:

          items:

            - description: aggre UFS PHY AXI clock

            - description: aggre USB3 PRIM AXI clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,eliza-aggre2-noc

    then:

      properties:

        clocks:

          items:

            - description: RPMH CC IPA clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,eliza-pcie-anoc

    then:

      properties:

        clocks:

          items:

            - description: aggre-NOC PCIe AXI clock

            - description: cfg-NOC PCIe a-NOC AHB clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,eliza-aggre1-noc

              - qcom,eliza-aggre2-noc

              - qcom,eliza-pcie-anoc

    then:

      required:

        - clocks

    else:

      properties:

        clocks: false



unevaluatedProperties: false



examples:

  - |

    gem_noc: interconnect@24100000 {

        compatible = "qcom,eliza-gem-noc";

        reg = <0x24100000 0x163080>;

        #interconnect-cells = <2>;

        qcom,bcm-voters = <&apps_bcm_voter>;

    };



    mc_virt: interconnect-2 {

        compatible = "qcom,eliza-mc-virt";

        #interconnect-cells = <2>;

        qcom,bcm-voters = <&apps_bcm_voter>;

    };



    aggre1_noc: interconnect@16e0000 {

        compatible = "qcom,eliza-aggre1-noc";

        reg = <0x16e0000 0x16400>;

        #interconnect-cells = <2>;

        clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;

        qcom,bcm-voters = <&apps_bcm_voter>;

    };

include/dt-bindings/interconnect/qcom,eliza-rpmh.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.

 */



#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H

#define __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H



#define MASTER_QSPI_0				0

#define MASTER_QUP_1				1

#define MASTER_UFS_MEM				2

#define MASTER_USB3_0				3

#define SLAVE_A1NOC_SNOC			4



#define MASTER_QUP_2				0

#define MASTER_CRYPTO				1

#define MASTER_IPA				2

#define MASTER_SOCCP_AGGR_NOC			3

#define MASTER_QDSS_ETR				4

#define MASTER_QDSS_ETR_1			5

#define MASTER_SDCC_1				6

#define MASTER_SDCC_2				7

#define SLAVE_A2NOC_SNOC			8



#define MASTER_QUP_CORE_1			0

#define MASTER_QUP_CORE_2			1

#define SLAVE_QUP_CORE_1			2

#define SLAVE_QUP_CORE_2			3



#define MASTER_CNOC_CFG				0

#define SLAVE_AHB2PHY_SOUTH			1

#define SLAVE_AHB2PHY_NORTH			2

#define SLAVE_CAMERA_CFG			3

#define SLAVE_CLK_CTL				4

#define SLAVE_CRYPTO_0_CFG			5

#define SLAVE_DISPLAY_CFG			6

#define SLAVE_GFX3D_CFG				7

#define SLAVE_I3C_IBI0_CFG			8

#define SLAVE_I3C_IBI1_CFG			9

#define SLAVE_IMEM_CFG				10

#define SLAVE_CNOC_MSS				11

#define SLAVE_PCIE_0_CFG			12

#define SLAVE_PRNG				13

#define SLAVE_QDSS_CFG				14

#define SLAVE_QSPI_0				15

#define SLAVE_QUP_1				16

#define SLAVE_QUP_2				17

#define SLAVE_SDCC_2				18

#define SLAVE_TCSR				19

#define SLAVE_TLMM				20

#define SLAVE_UFS_MEM_CFG			21

#define SLAVE_USB3_0				22

#define SLAVE_VENUS_CFG				23

#define SLAVE_VSENSE_CTRL_CFG			24

#define SLAVE_CNOC_MNOC_HF_CFG			25

#define SLAVE_CNOC_MNOC_SF_CFG			26

#define SLAVE_PCIE_ANOC_CFG			27

#define SLAVE_QDSS_STM				28

#define SLAVE_TCU				29



#define MASTER_GEM_NOC_CNOC			0

#define MASTER_GEM_NOC_PCIE_SNOC		1

#define SLAVE_AOSS				2

#define SLAVE_IPA_CFG				3

#define SLAVE_IPC_ROUTER_CFG			4

#define SLAVE_SOCCP				5

#define SLAVE_TME_CFG				6

#define SLAVE_APPSS				7

#define SLAVE_CNOC_CFG				8

#define SLAVE_DDRSS_CFG				9

#define SLAVE_BOOT_IMEM				10

#define SLAVE_IMEM				11

#define SLAVE_BOOT_IMEM_2			12

#define SLAVE_SERVICE_CNOC			13

#define SLAVE_PCIE_0				14

#define SLAVE_PCIE_1				15



#define MASTER_GPU_TCU				0

#define MASTER_SYS_TCU				1

#define MASTER_APPSS_PROC			2

#define MASTER_GFX3D				3

#define MASTER_LPASS_GEM_NOC			4

#define MASTER_MSS_PROC				5

#define MASTER_MNOC_HF_MEM_NOC			6

#define MASTER_MNOC_SF_MEM_NOC			7

#define MASTER_COMPUTE_NOC			8

#define MASTER_ANOC_PCIE_GEM_NOC		9

#define MASTER_SNOC_SF_MEM_NOC			10

#define MASTER_WLAN_Q6				11

#define MASTER_GIC				12

#define SLAVE_GEM_NOC_CNOC			13

#define SLAVE_LLCC				14

#define SLAVE_MEM_NOC_PCIE_SNOC			15



#define MASTER_LPIAON_NOC			0

#define SLAVE_LPASS_GEM_NOC			1



#define MASTER_LPASS_LPINOC			0

#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1



#define MASTER_LPASS_PROC			0

#define SLAVE_LPICX_NOC_LPIAON_NOC		1



#define MASTER_LLCC				0

#define SLAVE_EBI1				1



#define MASTER_CAMNOC_NRT_ICP_SF		0

#define MASTER_CAMNOC_RT_CDM_SF			1

#define MASTER_CAMNOC_SF			2

#define MASTER_VIDEO_MVP			3

#define MASTER_VIDEO_V_PROC			4

#define MASTER_CNOC_MNOC_SF_CFG			5

#define MASTER_CAMNOC_HF			6

#define MASTER_MDP				7

#define MASTER_CNOC_MNOC_HF_CFG			8

#define SLAVE_MNOC_SF_MEM_NOC			9

#define SLAVE_SERVICE_MNOC_SF			10

#define SLAVE_MNOC_HF_MEM_NOC			11

#define SLAVE_SERVICE_MNOC_HF			12



#define MASTER_CDSP_PROC			0

#define SLAVE_CDSP_MEM_NOC			1



#define MASTER_PCIE_ANOC_CFG			0

#define MASTER_PCIE_0				1

#define MASTER_PCIE_1				2

#define SLAVE_ANOC_PCIE_GEM_NOC			3

#define SLAVE_SERVICE_PCIE_ANOC			4



#define MASTER_A1NOC_SNOC			0

#define MASTER_A2NOC_SNOC			1

#define MASTER_CNOC_SNOC			2

#define MASTER_NSINOC_SNOC			3

#define SLAVE_SNOC_GEM_NOC_SF			4



#endif