Commit 831a8ac7 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Heiko Stuebner
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clk: rockchip: rk3588: Add PLL rate for 1500 MHz 



At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add
that frequency to the PLL table.

Signed-off-by: default avatarAlexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.kernel.org/r/20250408064612.41359-1-eagle.alexander923@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 0af2f6be

drivers/clk/rockchip/clk-rk3588.c

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { 
	RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),

	RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),

	RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),

	RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),

	RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),

	RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),

	RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),