Commit 8333f22e authored by Nicholas Carbones's avatar Nicholas Carbones Committed by Alex Deucher
Browse files

drm/amd/display: Query DC for gfx handling when setting linear tiling 



[Why]
Post-driver cases always use linear tiling yet gfx handling for this
case is improper, allowing for incorrect gfx structs to be populated and
used.

[How]
Query DC for the apporpriate linear tiling mode and populate the DCN
specific gfx version structs.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarNicholas Carbones <Nicholas.Carbones@amd.com>
Signed-off-by: default avatarChuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b034c5b0

drivers/gpu/drm/amd/display/dc/core/dc.c

+10 −0
Original line number Diff line number Diff line
@@ -2617,6 +2617,16 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) 
	dc->optimized_required = false;

}



void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info)

{

	if (!dc || !tiling_info)

		return;

	if (dc->res_pool && dc->res_pool->funcs && dc->res_pool->funcs->get_default_tiling_info) {

		dc->res_pool->funcs->get_default_tiling_info(tiling_info);

		return;

	}

}



bool dc_set_generic_gpio_for_stereo(bool enable,

		struct gpio_service *gpio_service)

{

drivers/gpu/drm/amd/display/dc/dc.h

+9 −0
Original line number Diff line number Diff line
@@ -1970,6 +1970,15 @@ void dc_plane_cm_retain(struct dc_plane_cm *cm); 
void dc_post_update_surfaces_to_stream(

		struct dc *dc);



/*

 * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling

 * description for (typically) linear surfaces.

 *

 * This is used by OS/DM paths that need a valid, fully-initialized tiling

 * description without hardcoding gfx-version specifics in the caller.

 */

void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info);



/**

 * struct dc_validation_set - Struct to store surface/stream associations for validation

 */

drivers/gpu/drm/amd/display/dc/inc/core_types.h

+1 −0
Original line number Diff line number Diff line
@@ -214,6 +214,7 @@ struct resource_funcs { 
            unsigned int index);



	void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);

	void (*get_default_tiling_info)(struct dc_tiling_info *tiling_info);

	void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);

	/*

	 * Get indicator of power from a context that went through full validation

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

+8 −1
Original line number Diff line number Diff line
@@ -1273,6 +1273,12 @@ static const struct dc_cap_funcs cap_funcs = { 
	.get_dcc_compression_cap = dcn10_get_dcc_compression_cap

};



void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info)

{

	tiling_info->gfxversion = DcGfxVersion9;

	tiling_info->gfx9.swizzle = DC_SW_LINEAR;

}



static const struct resource_funcs dcn10_res_pool_funcs = {

	.destroy = dcn10_destroy_resource_pool,

	.link_enc_create = dcn10_link_encoder_create,
@@ -1284,7 +1290,8 @@ static const struct resource_funcs dcn10_res_pool_funcs = { 
	.add_stream_to_ctx = dcn10_add_stream_to_ctx,

	.patch_unknown_plane_state = dcn10_patch_unknown_plane_state,

	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,

	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe

	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,

	.get_default_tiling_info = dcn10_get_default_tiling_info

};



static uint32_t read_pipe_fuses(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h

+2 −0
Original line number Diff line number Diff line
@@ -53,5 +53,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 


unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);



void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info);



#endif /* __DC_RESOURCE_DCN10_H__ */