Commit 837cc7f1 authored by Sunil Khatri's avatar Sunil Khatri Committed by Alex Deucher
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drm/amdgpu: add vcn_v1_0 ip dump support 



Add support of vcn ip dump in the devcoredump
for vcn_v1_0.

Signed-off-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 439c3b12

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+77 −1
Original line number Diff line number Diff line
@@ -45,6 +45,42 @@ 
#define mmUVD_REG_XX_MASK_1_0			0x05ac

#define mmUVD_REG_XX_MASK_1_0_BASE_IDX		1



static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = {

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),

	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

};



static int vcn_v1_0_stop(struct amdgpu_device *adev);

static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);

static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
@@ -90,6 +126,8 @@ static int vcn_v1_0_sw_init(void *handle) 
{

	struct amdgpu_ring *ring;

	int i, r;

	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);

	uint32_t *ptr;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* VCN DEC TRAP */
@@ -161,6 +199,14 @@ static int vcn_v1_0_sw_init(void *handle) 


	r = jpeg_v1_0_sw_init(handle);



	/* Allocate memory for VCN IP Dump buffer */

	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);

	if (!ptr) {

		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");

		adev->vcn.ip_dump = NULL;

	} else {

		adev->vcn.ip_dump = ptr;

	}

	return r;

}
@@ -184,6 +230,8 @@ static int vcn_v1_0_sw_fini(void *handle) 


	r = amdgpu_vcn_sw_fini(adev);



	kfree(adev->vcn.ip_dump);



	return r;

}
@@ -1877,6 +1925,34 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) 
	mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);

}



static void vcn_v1_0_dump_ip_state(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int i, j;

	bool is_powered;

	uint32_t inst_off;

	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);



	if (!adev->vcn.ip_dump)

		return;



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		if (adev->vcn.harvest_config & (1 << i))

			continue;



		inst_off = i * reg_count;

		/* mmUVD_POWER_STATUS is always readable and is first element of the array */

		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);

		is_powered = (adev->vcn.ip_dump[inst_off] &

				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;



		if (is_powered)

			for (j = 1; j < reg_count; j++)

				adev->vcn.ip_dump[inst_off + j] =

					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));

	}

}



static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {

	.name = "vcn_v1_0",

	.early_init = vcn_v1_0_early_init,
@@ -1895,7 +1971,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 
	.post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,

	.set_clockgating_state = vcn_v1_0_set_clockgating_state,

	.set_powergating_state = vcn_v1_0_set_powergating_state,

	.dump_ip_state = NULL,

	.dump_ip_state = vcn_v1_0_dump_ip_state,

	.print_ip_state = NULL,

};