Commit 8384087a authored by William Qiu's avatar William Qiu Committed by Conor Dooley
Browse files

riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC 



Add the quad spi controller node for the StarFive JH7110 SoC.

Co-developed-by: default avatarZiv Xu <ziv.xu@starfivetech.com>
Signed-off-by: default avatarZiv Xu <ziv.xu@starfivetech.com>
Signed-off-by: default avatarWilliam Qiu <william.qiu@starfivetech.com>
Reviewed-by: default avatarHal Feng <hal.feng@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent e7c304c0

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -185,6 +185,42 @@ &i2c6 { 
	status = "okay";

};



&qspi {

	#address-cells = <1>;

	#size-cells = <0>;

	status = "okay";



	nor_flash: flash@0 {

		compatible = "jedec,spi-nor";

		reg = <0>;

		cdns,read-delay = <5>;

		spi-max-frequency = <12000000>;

		cdns,tshsl-ns = <1>;

		cdns,tsd2d-ns = <1>;

		cdns,tchsh-ns = <1>;

		cdns,tslch-ns = <1>;



		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;



			spl@0 {

				reg = <0x0 0x80000>;

			};

			uboot-env@f0000 {

				reg = <0xf0000 0x10000>;

			};

			uboot@100000 {

				reg = <0x100000 0x400000>;

			};

			reserved-data@600000 {

				reg = <0x600000 0x1000000>;

			};

		};

	};

};



&spi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&spi0_pins>;

arch/riscv/boot/dts/starfive/jh7110.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -676,6 +676,25 @@ i2c6: i2c@12060000 { 
			status = "disabled";

		};



		qspi: spi@13010000 {

			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";

			reg = <0x0 0x13010000 0x0 0x10000>,

			      <0x0 0x21000000 0x0 0x400000>;

			interrupts = <25>;

			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,

				 <&syscrg JH7110_SYSCLK_QSPI_AHB>,

				 <&syscrg JH7110_SYSCLK_QSPI_APB>;

			clock-names = "ref", "ahb", "apb";

			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,

				 <&syscrg JH7110_SYSRST_QSPI_AHB>,

				 <&syscrg JH7110_SYSRST_QSPI_REF>;

			reset-names = "qspi", "qspi-ocp", "rstc_ref";

			cdns,fifo-depth = <256>;

			cdns,fifo-width = <4>;

			cdns,trigger-address = <0x0>;

			status = "disabled";

		};



		spi3: spi@12070000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x0 0x12070000 0x0 0x10000>;