Commit 839ff58e authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/boot: Remove all 40x platforms from boot 



Remove 40x platforms from the boot directory.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20240628121201.130802-2-mpe@ellerman.id.au
parent 47d13a26

arch/powerpc/boot/4xx.c

+0 −266
Original line number Diff line number Diff line
@@ -253,7 +253,6 @@ void ibm4xx_denali_fixup_memsize(void) 
	dt_fixup_memory(0, memsize);

}



#define SPRN_DBCR0_40X 0x3F2

#define SPRN_DBCR0_44X 0x134

#define DBCR0_RST_SYSTEM 0x30000000
@@ -270,18 +269,6 @@ void ibm44x_dbcr_reset(void) 


}



void ibm40x_dbcr_reset(void)

{

	unsigned long tmp;



	asm volatile (

		"mfspr	%0,%1\n"

		"oris	%0,%0,%2@h\n"

		"mtspr	%1,%0"

		: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)

		);

}



#define EMAC_RESET 0x20000000

void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)

{
@@ -544,256 +531,3 @@ void ibm440spe_fixup_clocks(unsigned int sys_clk, 
	eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);

	eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);

}
 


void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)

{

	u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);

	u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);

	u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);

	u32 psr = mfdcr(DCRN_405_CPC0_PSR);

	u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;

	u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;



	fwdv = (8 - ((pllmr & 0xe0000000) >> 29));

	fbdv = (pllmr & 0x1e000000) >> 25;

	if (fbdv == 0)

		fbdv = 16;

	cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */

	opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */

	ppdv = ((pllmr & 0x00006000) >> 13) + 1; /* PLB:PCI */

	epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */

	udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;



	/* check for 405GPr */

	if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {

		fwdvb = 8 - (pllmr & 0x00000007);

		if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */

			if (psr & 0x00000020) /* New mode enable */

				m = fwdvb * 2 * ppdv;

			else

				m = fwdvb * cbdv * ppdv;

		else if (psr & 0x00000020) /* New mode enable */

			if (psr & 0x00000800) /* PerClk synch mode */

				m = fwdvb * 2 * epdv;

			else

				m = fbdv * fwdv;

		else if (epdv == fbdv)

			m = fbdv * cbdv * epdv;

		else

			m = fbdv * fwdvb * cbdv;



		cpu = sys_clk * m / fwdv;

		plb = sys_clk * m / (fwdvb * cbdv);

	} else {

		m = fwdv * fbdv * cbdv;

		cpu = sys_clk * m / fwdv;

		plb = cpu / cbdv;

	}

	opb = plb / opdv;

	ebc = plb / epdv;



	if (cpc0_cr0 & 0x80)

		/* uart0 uses the external clock */

		uart0 = ser_clk;

	else

		uart0 = cpu / udiv;



	if (cpc0_cr0 & 0x40)

		/* uart1 uses the external clock */

		uart1 = ser_clk;

	else

		uart1 = cpu / udiv;



	/* setup the timebase clock to tick at the cpu frequency */

	cpc0_cr1 = cpc0_cr1 & ~0x00800000;

	mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);

	tb = cpu;



	dt_fixup_cpu_clocks(cpu, tb, 0);

	dt_fixup_clock("/plb", plb);

	dt_fixup_clock("/plb/opb", opb);

	dt_fixup_clock("/plb/ebc", ebc);

	dt_fixup_clock("/plb/opb/serial@ef600300", uart0);

	dt_fixup_clock("/plb/opb/serial@ef600400", uart1);

}





void ibm405ep_fixup_clocks(unsigned int sys_clk)

{

	u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);

	u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);

	u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);

	u32 cpu, plb, opb, ebc, uart0, uart1;

	u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;

	u32 pllmr0_ccdv, tb, m;



	fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);

	fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);

	fbdv = (pllmr1 & 0x00f00000) >> 20;

	if (fbdv == 0)

		fbdv = 16;



	cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */

	epdv = ((pllmr0 & 0x00000300) >> 8) + 2;  /* PLB:EBC */

	opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */



	m = fbdv * fwdvb;



	pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;

	if (pllmr1 & 0x80000000)

		cpu = sys_clk * m / (fwdva * pllmr0_ccdv);

	else

		cpu = sys_clk / pllmr0_ccdv;



	plb = cpu / cbdv;

	opb = plb / opdv;

	ebc = plb / epdv;

	tb = cpu;

	uart0 = cpu / (cpc0_ucr & 0x0000007f);

	uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);



	dt_fixup_cpu_clocks(cpu, tb, 0);

	dt_fixup_clock("/plb", plb);

	dt_fixup_clock("/plb/opb", opb);

	dt_fixup_clock("/plb/ebc", ebc);

	dt_fixup_clock("/plb/opb/serial@ef600300", uart0);

	dt_fixup_clock("/plb/opb/serial@ef600400", uart1);

}



static u8 ibm405ex_fwdv_multi_bits[] = {

	/* values for:  1 - 16 */

	0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,

	0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03

};



u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)

{

	u32 index;



	for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)

		if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])

			return index + 1;



	return 0;

}



static u8 ibm405ex_fbdv_multi_bits[] = {

	/* values for:  1 - 100 */

	0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,

	0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,

	0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,

	0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,

	0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,

	0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,

	0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,

	0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,

	0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,

	0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,

	/* values for:  101 - 200 */

	0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,

	0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,

	0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,

	0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,

	0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,

	0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,

	0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,

	0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,

	0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,

	0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,

	/* values for:  201 - 255 */

	0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,

	0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,

	0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,

	0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,

	0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,

	0x03, 0x87, 0x0f, 0x9f, 0x3f  /* END */

};



u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)

{

	u32 index;



	for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)

		if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])

			return index + 1;



	return 0;

}



void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)

{

	/* PLL config */

	u32 pllc  = CPR0_READ(DCRN_CPR0_PLLC);

	u32 plld  = CPR0_READ(DCRN_CPR0_PLLD);

	u32 cpud  = CPR0_READ(DCRN_CPR0_PRIMAD);

	u32 plbd  = CPR0_READ(DCRN_CPR0_PRIMBD);

	u32 opbd  = CPR0_READ(DCRN_CPR0_OPBD);

	u32 perd  = CPR0_READ(DCRN_CPR0_PERD);



	/* Dividers */

	u32 fbdv   = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));



	u32 fwdva  = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));



	u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);



	/* PLBDV0 is hardwared to 010. */

	u32 plbdv0 = 2;

	u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);



	u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);



	u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);



	/* Resulting clocks */

	u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;



	/* PLL's VCO is the source for primary forward ? */

	if (pllc & 0x40000000) {

		u32 m;



		/* Feedback path */

		switch ((pllc >> 24) & 7) {

		case 0:

			/* PLLOUTx */

			m = fbdv;

			break;

		case 1:

			/* CPU */

			m = fbdv * fwdva * cpudv0;

			break;

		case 5:

			/* PERClk */

			m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;

			break;

		default:

			printf("WARNING ! Invalid PLL feedback source !\n");

			goto bypass;

		}



		vco = (unsigned int)(sys_clk * m);

	} else {

bypass:

		/* Bypass system PLL */

		vco = 0;

	}



	/* CPU = VCO / ( FWDVA x CPUDV0) */

	cpu = vco / (fwdva * cpudv0);

	/* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */

	plb = vco / (fwdva * plb2xdv0 * plbdv0);

	/* OPB = PLB / OPBDV0 */

	opb = plb / opbdv0;

	/* EBC = OPB / PERDV0 */

	ebc = opb / perdv0;



	tb = cpu;

	uart0 = uart1 = uart_clk;



	dt_fixup_cpu_clocks(cpu, tb, 0);

	dt_fixup_clock("/plb", plb);

	dt_fixup_clock("/plb/opb", opb);

	dt_fixup_clock("/plb/opb/ebc", ebc);

	dt_fixup_clock("/plb/opb/serial@ef600200", uart0);

	dt_fixup_clock("/plb/opb/serial@ef600300", uart1);

}

arch/powerpc/boot/4xx.h

+0 −4
Original line number Diff line number Diff line
@@ -12,13 +12,9 @@ void ibm4xx_sdram_fixup_memsize(void); 
void ibm440spe_fixup_memsize(void);

void ibm4xx_denali_fixup_memsize(void);

void ibm44x_dbcr_reset(void);

void ibm40x_dbcr_reset(void);

void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);

void ibm4xx_fixup_ebc_ranges(const char *ebc);



void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);

void ibm405ep_fixup_clocks(unsigned int sys_clk);

void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk);

void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);

void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,

			   unsigned int tmr_clk);

arch/powerpc/boot/Makefile

+0 −11
Original line number Diff line number Diff line
@@ -54,10 +54,8 @@ endif 


$(obj)/4xx.o: BOOTTARGETFLAGS += -mcpu=405

$(obj)/ebony.o: BOOTTARGETFLAGS += -mcpu=440

$(obj)/cuboot-hotfoot.o: BOOTTARGETFLAGS += -mcpu=405

$(obj)/cuboot-taishan.o: BOOTTARGETFLAGS += -mcpu=440

$(obj)/cuboot-katmai.o: BOOTTARGETFLAGS += -mcpu=440

$(obj)/cuboot-acadia.o: BOOTTARGETFLAGS += -mcpu=405

$(obj)/treeboot-iss4xx.o: BOOTTARGETFLAGS += -mcpu=405

$(obj)/treeboot-currituck.o: BOOTTARGETFLAGS += -mcpu=405

$(obj)/treeboot-akebono.o: BOOTTARGETFLAGS += -mcpu=405
@@ -146,7 +144,6 @@ src-wlib-$(CONFIG_PPC_POWERNV) += opal-calls.S opal.c 
ifndef CONFIG_PPC64_BOOT_WRAPPER

src-wlib-y += crtsavres.S

endif

src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c

src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c

src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c

src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
@@ -154,9 +151,6 @@ src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c 
src-wlib-$(CONFIG_CPM) += cpm-serial.c



src-plat-y := of.c epapr.c

src-plat-$(CONFIG_40x) += fixed-head.S cuboot-hotfoot.c \

				cuboot-acadia.c \

				cuboot-kilauea.c simpleboot.c

src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \

				cuboot-bamboo.c cuboot-sam440ep.c \

				cuboot-sequoia.c cuboot-rainier.c \
@@ -300,11 +294,6 @@ image-$(CONFIG_EPAPR_BOOT) += zImage.epapr 
# Boards with newish u-boot firmware can use the uImage target above

#



# Board ports in arch/powerpc/platform/40x/Kconfig

image-$(CONFIG_HOTFOOT)			+= cuImage.hotfoot

image-$(CONFIG_ACADIA)			+= cuImage.acadia

image-$(CONFIG_OBS600)			+= uImage.obs600



# Board ports in arch/powerpc/platform/44x/Kconfig

image-$(CONFIG_EBONY)			+= treeImage.ebony cuImage.ebony

image-$(CONFIG_BAMBOO)			+= treeImage.bamboo cuImage.bamboo

arch/powerpc/boot/cuboot-acadia.c

deleted100644 → 0
+0 −171
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Old U-boot compatibility for Acadia

 *

 * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>

 *

 * Copyright 2008 IBM Corporation

 */



#include "ops.h"

#include "io.h"

#include "dcr.h"

#include "stdio.h"

#include "4xx.h"

#include "44x.h"

#include "cuboot.h"



#define TARGET_4xx

#include "ppcboot.h"



static bd_t bd;



#define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */



#define PLLC_SRC_MASK	       0x20000000     /* PLL feedback source */



#define PLLD_FBDV_MASK	       0x1F000000     /* PLL feedback divider value */

#define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */

#define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */



#define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */

#define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */

#define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */

#define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */



#define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */

#define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */

#define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */

#define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */



static void get_clocks(void)

{

	unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;

	unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;

	unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;

	unsigned long div;		/* total divisor udiv * bdiv */

	unsigned long umin;		/* minimum udiv	*/

	unsigned short diff;		/* smallest diff */

	unsigned long udiv;		/* best udiv */

	unsigned short idiff;		/* current diff */

	unsigned short ibdiv;		/* current bdiv */

	unsigned long est;		/* current estimate */

	unsigned long baud;

	void *np;



	/* read the sysclk value from the CPLD */

	sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;



	/*

	 * Read PLL Mode registers

	 */

	cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);

	cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);



	/*

	 * Determine forward divider A

	 */

	pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);



	/*

	 * Determine forward divider B

	 */

	pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);

	if (pllFwdDivB == 0)

		pllFwdDivB = 8;



	/*

	 * Determine FBK_DIV.

	 */

	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);

	if (pllFbkDiv == 0)

		pllFbkDiv = 256;



	/*

	 * Read CPR_PRIMAD register

	 */

	cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);



	/*

	 * Determine PLB_DIV.

	 */

	pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);

	if (pllPlbDiv == 0)

		pllPlbDiv = 16;



	/*

	 * Determine EXTBUS_DIV.

	 */

	pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);

	if (pllExtBusDiv == 0)

		pllExtBusDiv = 16;



	/*

	 * Determine OPB_DIV.

	 */

	pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);

	if (pllOpbDiv == 0)

		pllOpbDiv = 16;



	/* There is a bug in U-Boot that prevents us from using

	 * bd.bi_opbfreq because U-Boot doesn't populate it for

	 * 405EZ.  We get to calculate it, yay!

	 */

	freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;



	freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;



	plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?

					   pllFwdDivB : pllFwdDiv) *

		    pllFbkDiv) / pllFwdDivB);



	np = find_node_by_alias("serial0");

	if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))

		fatal("no current-speed property\n\r");



	udiv = 256;			/* Assume lowest possible serial clk */

	div = plloutb / (16 * baud); /* total divisor */

	umin = (plloutb / freqOPB) << 1;	/* 2 x OPB divisor */

	diff = 256;			/* highest possible */



	/* i is the test udiv value -- start with the largest

	 * possible (256) to minimize serial clock and constrain

	 * search to umin.

	 */

	for (i = 256; i > umin; i--) {

		ibdiv = div / i;

		est = i * ibdiv;

		idiff = (est > div) ? (est-div) : (div-est);

		if (idiff == 0) {

			udiv = i;

			break;      /* can't do better */

		} else if (idiff < diff) {

			udiv = i;       /* best so far */

			diff = idiff;   /* update lowest diff*/

		}

	}

	freqUART = plloutb / udiv;



	dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);

	dt_fixup_clock("/plb/ebc", freqEBC);

	dt_fixup_clock("/plb/opb", freqOPB);

	dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);

	dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);

}



static void acadia_fixups(void)

{

	dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);

	get_clocks();

	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);

}

	

void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,

		unsigned long r6, unsigned long r7)

{

	CUBOOT_INIT();

	platform_ops.fixups = acadia_fixups;

	platform_ops.exit = ibm40x_dbcr_reset;

	fdt_init(_dtb_start);

	serial_console_init();

}

arch/powerpc/boot/cuboot-hotfoot.c

deleted100644 → 0
+0 −139
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Old U-boot compatibility for Esteem 195E Hotfoot CPU Board

 *

 * Author: Solomon Peachy <solomon@linux-wlan.com>

 */



#include "ops.h"

#include "stdio.h"

#include "reg.h"

#include "dcr.h"

#include "4xx.h"

#include "cuboot.h"



#define TARGET_4xx

#define TARGET_HOTFOOT



#include "ppcboot-hotfoot.h"



static bd_t bd;



#define NUM_REGS 3



static void hotfoot_fixups(void)

{

	u32 uart = mfdcr(DCRN_CPC0_UCR) & 0x7f;



	dt_fixup_memory(bd.bi_memstart, bd.bi_memsize); 



	dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_procfreq, 0);

	dt_fixup_clock("/plb", bd.bi_plb_busfreq);

	dt_fixup_clock("/plb/opb", bd.bi_opbfreq);

	dt_fixup_clock("/plb/ebc", bd.bi_pci_busfreq);

	dt_fixup_clock("/plb/opb/serial@ef600300", bd.bi_procfreq / uart); 

	dt_fixup_clock("/plb/opb/serial@ef600400", bd.bi_procfreq / uart); 

	

	dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);

	dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);



	/* Is this a single eth/serial board? */

	if ((bd.bi_enet1addr[0] == 0) && 

	    (bd.bi_enet1addr[1] == 0) &&

	    (bd.bi_enet1addr[2] == 0) &&

	    (bd.bi_enet1addr[3] == 0) &&

	    (bd.bi_enet1addr[4] == 0) &&

	    (bd.bi_enet1addr[5] == 0)) {

		void *devp;



		printf("Trimming devtree for single serial/eth board\n");



		devp = finddevice("/plb/opb/serial@ef600300");

		if (!devp)

			fatal("Can't find node for /plb/opb/serial@ef600300");

		del_node(devp);



		devp = finddevice("/plb/opb/ethernet@ef600900");

		if (!devp)

			fatal("Can't find node for /plb/opb/ethernet@ef600900");

		del_node(devp);

	}



	ibm4xx_quiesce_eth((u32 *)0xef600800, (u32 *)0xef600900);



	/* Fix up flash size in fdt for 4M boards. */

	if (bd.bi_flashsize < 0x800000) {

		u32 regs[NUM_REGS];

		void *devp = finddevice("/plb/ebc/nor_flash@0");

		if (!devp)

			fatal("Can't find FDT node for nor_flash!??");



		printf("Fixing devtree for 4M Flash\n");

		

		/* First fix up the base address */

		getprop(devp, "reg", regs, sizeof(regs));

		regs[0] = 0;

		regs[1] = 0xffc00000;

		regs[2] = 0x00400000;

		setprop(devp, "reg", regs, sizeof(regs));

		

		/* Then the offsets */

		devp = finddevice("/plb/ebc/nor_flash@0/partition@0");

		if (!devp)

			fatal("Can't find FDT node for partition@0");

		getprop(devp, "reg", regs, 2*sizeof(u32));

		regs[0] -= 0x400000;

		setprop(devp, "reg", regs,  2*sizeof(u32));



		devp = finddevice("/plb/ebc/nor_flash@0/partition@1");

		if (!devp)

			fatal("Can't find FDT node for partition@1");

		getprop(devp, "reg", regs, 2*sizeof(u32));

		regs[0] -= 0x400000;

		setprop(devp, "reg", regs,  2*sizeof(u32));



		devp = finddevice("/plb/ebc/nor_flash@0/partition@2");

		if (!devp)

			fatal("Can't find FDT node for partition@2");

		getprop(devp, "reg", regs, 2*sizeof(u32));

		regs[0] -= 0x400000;

		setprop(devp, "reg", regs,  2*sizeof(u32));



		devp = finddevice("/plb/ebc/nor_flash@0/partition@3");

		if (!devp)

			fatal("Can't find FDT node for partition@3");

		getprop(devp, "reg", regs, 2*sizeof(u32));

		regs[0] -= 0x400000;

		setprop(devp, "reg", regs,  2*sizeof(u32));



		devp = finddevice("/plb/ebc/nor_flash@0/partition@4");

		if (!devp)

			fatal("Can't find FDT node for partition@4");

		getprop(devp, "reg", regs, 2*sizeof(u32));

		regs[0] -= 0x400000;

		setprop(devp, "reg", regs,  2*sizeof(u32));



		devp = finddevice("/plb/ebc/nor_flash@0/partition@6");

		if (!devp)

			fatal("Can't find FDT node for partition@6");

		getprop(devp, "reg", regs, 2*sizeof(u32));

		regs[0] -= 0x400000;

		setprop(devp, "reg", regs,  2*sizeof(u32));



		/* Delete the FeatFS node */

		devp = finddevice("/plb/ebc/nor_flash@0/partition@5");

		if (!devp)

			fatal("Can't find FDT node for partition@5");

		del_node(devp);

	}

}



void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,

		   unsigned long r6, unsigned long r7)

{

	CUBOOT_INIT();

	platform_ops.fixups = hotfoot_fixups;

        platform_ops.exit = ibm40x_dbcr_reset;

	fdt_init(_dtb_start);

	serial_console_init();

}