Commit 83c4e3c3 authored by Tudor Ambarus's avatar Tudor Ambarus Committed by Krzysztof Kozlowski
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dt-bindings: firmware: google,gs101-acpm-ipc: add ACPM clocks



The firmware exposes clocks that can be controlled via the
Alive Clock and Power Manager (ACPM) interface.

Make the ACPM node a clock provider by adding the mandatory
"#clock-cells" property, which allows devices to reference its
clock outputs.

Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20251010-acpm-clk-v6-1-321ee8826fd4@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 3a866087
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+11 −0
Original line number Diff line number Diff line
@@ -24,6 +24,15 @@ properties:
  compatible:
    const: google,gs101-acpm-ipc

  "#clock-cells":
    const: 1
    description:
      Clocks that are variable and index based. These clocks don't provide
      an entire range of values between the limits but only discrete points
      within the range. The firmware also manages the voltage scaling
      appropriately with the clock scaling. The argument is the ID of the
      clock contained by the firmware messages.

  mboxes:
    maxItems: 1

@@ -45,6 +54,7 @@ properties:

required:
  - compatible
  - "#clock-cells"
  - mboxes
  - shmem

@@ -56,6 +66,7 @@ examples:

    power-management {
        compatible = "google,gs101-acpm-ipc";
        #clock-cells = <1>;
        mboxes = <&ap2apm_mailbox>;
        shmem = <&apm_sram>;

+26 −0
Original line number Diff line number Diff line
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright 2025 Linaro Ltd.
 *
 * Device Tree binding constants for Google gs101 ACPM clock controller.
 */

#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H
#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H

#define GS101_CLK_ACPM_DVFS_MIF				0
#define GS101_CLK_ACPM_DVFS_INT				1
#define GS101_CLK_ACPM_DVFS_CPUCL0			2
#define GS101_CLK_ACPM_DVFS_CPUCL1			3
#define GS101_CLK_ACPM_DVFS_CPUCL2			4
#define GS101_CLK_ACPM_DVFS_G3D				5
#define GS101_CLK_ACPM_DVFS_G3DL2			6
#define GS101_CLK_ACPM_DVFS_TPU				7
#define GS101_CLK_ACPM_DVFS_INTCAM			8
#define GS101_CLK_ACPM_DVFS_TNR				9
#define GS101_CLK_ACPM_DVFS_CAM				10
#define GS101_CLK_ACPM_DVFS_MFC				11
#define GS101_CLK_ACPM_DVFS_DISP			12
#define GS101_CLK_ACPM_DVFS_BO				13

#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */