Merge tag 'amd-drm-next-6.20-2026-01-09' of...

    CP

      Command Processor

    CPC

      Command Processor Compute

    CPF

      Command Processor Fetch

    CPG

      Command Processor Graphics

    CPLIB

      Content Protection Library

    GMC

      Graphic Memory Controller

    GPR

      General Purpose Register

    GPUVM

      GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple

      virtual address spaces that can be in flight at any given time.  These

      table for use by the kernel driver or into per process GPUVM page tables

      for application usage.

    GWS

      Global Wave Sync

    IH

      Interrupt Handler

    IV

      Interrupt Vector

    HQD

      Hardware Queue Descriptor

    PA

      Primitive Assembler / Physical Address

    PDE

      Page Directory Entry

    PFP

      Pre-Fetch Parser (Graphics)

    PPLib

      PowerPlay Library - PowerPlay is the power management component.

    PRT

      Partially Resident Texture (also known as sparse residency)

    PSP

        Platform Security Processor

    PTE

      Page Table Entry

    RB

      Render Backends. Some people called it ROPs.

    TC

      Texture Cache

    TCP (AMDGPU)

      Texture Cache per Pipe. Even though the name "Texture" is part of this

      acronym, the TCP represents the path to memory shaders; i.e., it is not

      related to texture. The name is a leftover from older designs where shader

      stages had different cache designs; it refers to the L1 cache in older

      architectures.

    TMR

      Trusted Memory Region

    TMZ

      Trusted Memory Zone

    TOC

      Table of Contents

    UMC

      Unified Memory Controller

    UMSCH

      User Mode Scheduler

    UTC (AMDGPU)

      Unified Translation Cache. UTC is equivalent to TLB. You might see a

      variation of this acronym with L at the end, i.e., UTCL followed by a

      number; L means the cache level (e.g., UTCL1 and UTCL2).

    UVD

      Unified Video Decoder

    TMDS

      Transition-Minimized Differential Signaling

    TMZ

      Trusted Memory Zone

    TTU

      Time to Underflow

    decode.  It's exposed to userspace for user mode drivers (VA-API,

    OpenMAX, etc.)

It is important to note that these blocks can interact with each other. The

picture below illustrates some of the components and their interconnection:

.. kernel-figure:: amd_overview_block.svg

In the diagram, memory-related blocks are shown in green. Notice that specific

IPs have a green square that represents a small hardware block named 'hub',

which is responsible for interfacing with memory. All memory hubs are connected

in the UMCs, which in turn are connected to memory blocks. As a note,

pre-vega devices have a dedicated block for the Graphic Memory Controller

(GMC), which was replaced by UMC and hubs in new architectures. In the driver

code, you can identify this component by looking for the suffix hub, for

example: gfxhub, dchub, mmhub, vmhub, etc. Keep in mind that the component's

interaction with the memory block may vary across architectures. For example,

on Navi and newer, GC and SDMA are both attached to GCHUB; on pre-Navi, SDMA

goes through MMHUB; VCN, JPEG, and VPE go through MMHUB; DCN goes through

DCHUB.

There is some protection for certain memory elements, and the PSP plays an

essential role in this area. When a specific firmware is loaded into memory,

the PSP takes steps to ensure it has a valid signature. It also stores firmware

images in a protected memory area named Trusted Memory Area (TMR), so the OS or

driver can't corrupt them at runtime. Another use of PSP is to support Trusted

Applications (TA), which are basically small applications that run on the

trusted processor and handles a trusted operation (e.g., HDCP). PSP is also

used for encrypted memory for content protection via Trusted Memory Zone (TMZ).

Another critical IP is the SMU. It handles reset distribution, as well as

clock, thermal, and power management for all IPs on the SoC. SMU also helps to

balance performance and power consumption.

.. _pipes-and-queues-description:

GFX, Compute, and SDMA Overall Behavior

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c

   :doc: smartshift_bias

UMA Carveout

============

Some versions of Atom ROM expose available options for the VRAM carveout sizes,

and allow changes to the carveout size via the ATCS function code 0xA on supported

BIOS implementations.

For those platforms, users can use the following files under uma/ to set the

carveout size, in a way similar to what Windows users can do in the "Tuning"

tab in AMD Adrenalin.

Note that for BIOS implementations that don't support this, these files will not

be created at all.

uma/carveout_options

--------------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: uma/carveout_options

uma/carveout

--------------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: uma/carveout