Commit 83f00078 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xe-fixes-2024-10-17' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes 



Driver Changes:
- New workaround to Xe2 (Aradhya)
- Fix unbalanced rpm put (Matthew Auld)
- Remove fragile lock optimization (Matthew Brost)
- Fix job release, delegating it to the drm scheduler (Matthew Brost)
- Fix timestamp bit width for Xe2 (Lucas)
- Fix external BO's dma-resv usag (Matthew Brost)
- Fix returning success for timeout in wait_token (Nirmoy)
- Initialize fence to avoid it being detected as signaled (Matthew Auld)
- Improve cache flush for BMG (Matthew Auld)
- Don't allow hflip for tile4 framebuffer on Xe2 (Juha-Pekka)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/jkldrex5733ldxrla75b4ayvhujjhw2kccmasl5rotoufoacj4@pkvlrrv4orc7
parents 49ff3e79 ffafd126

drivers/gpu/drm/i915/display/intel_fb.c

+13 −0
Original line number Diff line number Diff line
@@ -438,6 +438,19 @@ bool intel_fb_needs_64k_phys(u64 modifier) 
				      INTEL_PLANE_CAP_NEED64K_PHYS);

}



/**

 * intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type

 * @modifier: Modifier to check

 *

 * Returns:

 * Returns %true if @modifier is a tile4 modifier.

 */

bool intel_fb_is_tile4_modifier(u64 modifier)

{

	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,

				      INTEL_PLANE_CAP_TILING_4);

}



static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,

					     u8 display_ver_from, u8 display_ver_until)

{

drivers/gpu/drm/i915/display/intel_fb.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier); 
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);

bool intel_fb_is_mc_ccs_modifier(u64 modifier);

bool intel_fb_needs_64k_phys(u64 modifier);

bool intel_fb_is_tile4_modifier(u64 modifier);



bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);

int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);

drivers/gpu/drm/i915/display/skl_universal_plane.c

+11 −0
Original line number Diff line number Diff line
@@ -1591,6 +1591,17 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 
		return -EINVAL;

	}



	/*

	 * Display20 onward tile4 hflip is not supported

	 */

	if (rotation & DRM_MODE_REFLECT_X &&

	    intel_fb_is_tile4_modifier(fb->modifier) &&

	    DISPLAY_VER(dev_priv) >= 20) {

		drm_dbg_kms(&dev_priv->drm,

			    "horizontal flip is not supported with tile4 surface formats\n");

		return -EINVAL;

	}



	if (drm_rotation_90_or_270(rotation)) {

		if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {

			drm_dbg_kms(&dev_priv->drm,

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+0 −3
Original line number Diff line number Diff line
@@ -393,9 +393,6 @@ 


#define XE2_GLOBAL_INVAL			XE_REG(0xb404)



#define SCRATCH1LPFC				XE_REG(0xb474)

#define   EN_L3_RW_CCS_CACHE_FLUSH		REG_BIT(0)



#define XE2LPM_L3SQCREG2			XE_REG_MCR(0xb604)



#define XE2LPM_L3SQCREG3			XE_REG_MCR(0xb608)

drivers/gpu/drm/xe/xe_device.c

+2 −2
Original line number Diff line number Diff line
@@ -980,13 +980,13 @@ void xe_device_declare_wedged(struct xe_device *xe) 
		return;

	}



	xe_pm_runtime_get_noresume(xe);



	if (drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe)) {

		drm_err(&xe->drm, "Failed to register xe_device_wedged_fini clean-up. Although device is wedged.\n");

		return;

	}



	xe_pm_runtime_get_noresume(xe);



	if (!atomic_xchg(&xe->wedged.flag, 1)) {

		xe->needs_flr_on_fini = true;

		drm_err(&xe->drm,