Commit 83f41517 authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe/lnl: Drop pre-production workaround support 



LNL has been out long enough that all of our internal usage of
pre-production hardware has been phased out and we no longer need to
maintain workarounds that were exclusive to pre-production parts.

Production LNL hardware always has B0 or later steppings for both
graphics and media IP.  Eliminate all workarounds that were exclusive to
A-step hardware and set the 'has_prod_wa_only' device flag for LNL to
make sure we warn and taint if someone tries to load the driver on an
old pre-production part.

Bspec: 70821
Reviewed-by: default avatarDnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patch.msgid.link/20251212181411.294854-4-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent 7ef2d25e

drivers/gpu/drm/xe/xe_guc_ads.c

+1 −1
Original line number Diff line number Diff line
@@ -317,7 +317,7 @@ static void guc_waklv_init(struct xe_guc_ads *ads) 
	offset = guc_ads_waklv_offset(ads);

	remain = guc_ads_waklv_size(ads);



	if (XE_GT_WA(gt, 14019882105) || XE_GT_WA(gt, 16021333562))

	if (XE_GT_WA(gt, 16021333562))

		guc_waklv_enable(ads, NULL, 0, &offset, &remain,

				 GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED);

	if (XE_GT_WA(gt, 18024947630))

drivers/gpu/drm/xe/xe_pci.c

+0 −1
Original line number Diff line number Diff line
@@ -347,7 +347,6 @@ static const struct xe_device_desc lnl_desc = { 
	.dma_mask_size = 46,

	.has_display = true,

	.has_flat_ccs = 1,

	.has_pre_prod_wa = 1,

	.has_pxp = true,

	.has_mem_copy_instr = true,

	.max_gt_per_tile = 2,

drivers/gpu/drm/xe/xe_ring_ops.c

+0 −18
Original line number Diff line number Diff line
@@ -211,22 +211,6 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) 
	return emit_pipe_control(dw, i, flags0, flags1, 0, 0);

}



static int emit_pipe_control_to_ring_end(struct xe_exec_queue *q, u32 *dw, int i)

{

	struct xe_hw_engine *hwe = q->hwe;



	if (hwe->class != XE_ENGINE_CLASS_RENDER)

		return i;



	xe_gt_assert(q->gt, !xe_exec_queue_is_multi_queue(q));



	if (XE_GT_WA(hwe->gt, 16020292621))

		i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_LRI_POST_SYNC,

				      RING_NOPID(hwe->mmio_base).addr, 0);



	return i;

}



static int emit_pipe_imm_ggtt(struct xe_exec_queue *q, u32 addr, u32 value,

			      bool stall_only, u32 *dw, int i)

{
@@ -413,8 +397,6 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, 


	i = emit_user_interrupt(dw, i);



	i = emit_pipe_control_to_ring_end(job->q, dw, i);



	xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);



	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));

drivers/gpu/drm/xe/xe_wa.c

+0 −45
Original line number Diff line number Diff line
@@ -217,20 +217,6 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))

	},



	/* Xe2_LPG */



	{ XE_RTP_NAME("16020975621"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),

	  XE_RTP_ACTIONS(SET(XEHP_SLICE_UNIT_LEVEL_CLKGATE, SBEUNIT_CLKGATE_DIS))

	},

	{ XE_RTP_NAME("14018157293"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)),

	  XE_RTP_ACTIONS(SET(XEHPC_L3CLOS_MASK(0), ~0),

			 SET(XEHPC_L3CLOS_MASK(1), ~0),

			 SET(XEHPC_L3CLOS_MASK(2), ~0),

			 SET(XEHPC_L3CLOS_MASK(3), ~0))

	},



	/* Xe2_LPM */



	{ XE_RTP_NAME("14017421178"),
@@ -509,11 +495,6 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS))

	},

	{ XE_RTP_NAME("14018957109"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN5, DISABLE_SAMPLE_G_PERFORMANCE))

	},

	{ XE_RTP_NAME("14020338487"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS))
@@ -523,11 +504,6 @@ static const struct xe_rtp_entry_sr engine_was[] = { 
		       FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(ROW_CHICKEN4, DISABLE_TDL_PUSH))

	},

	{ XE_RTP_NAME("14019322943"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, TGM_WRITE_EOM_FORCE))

	},

	{ XE_RTP_NAME("14018471104"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)),

	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL))
@@ -804,17 +780,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 


	/* Xe2_LPG */



	{ XE_RTP_NAME("16020518922"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(FF_MODE,

			     DIS_TE_AUTOSTRIP |

			     DIS_MESH_PARTIAL_AUTOSTRIP |

			     DIS_MESH_AUTOSTRIP),

			 SET(VFLSKPD,

			     DIS_PARTIAL_AUTOSTRIP |

			     DIS_AUTOSTRIP))

	},

	{ XE_RTP_NAME("14019386621"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE))
@@ -823,20 +788,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},

	{ XE_RTP_NAME("14020013138"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))

	},

	{ XE_RTP_NAME("14019988906"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))

	},

	{ XE_RTP_NAME("16020183090"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))

	},

	{ XE_RTP_NAME("18033852989"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))

drivers/gpu/drm/xe/xe_wa_oob.rules

+1 −5
Original line number Diff line number Diff line
@@ -16,15 +16,11 @@ 
16017236439	PLATFORM(PVC)

14019821291	MEDIA_VERSION_RANGE(1300, 2000)

14015076503	MEDIA_VERSION(1300)

16020292621	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)

14018913170	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)

		MEDIA_VERSION(2000), GRAPHICS_STEP(A0, A1)

		GRAPHICS_VERSION_RANGE(1270, 1274)

14018913170	GRAPHICS_VERSION_RANGE(1270, 1274)

		MEDIA_VERSION(1300)

		PLATFORM(DG2)

14018094691	GRAPHICS_VERSION_RANGE(2001, 2002)

		GRAPHICS_VERSION(2004)

14019882105	GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)

18024947630	GRAPHICS_VERSION(2001)

		GRAPHICS_VERSION(2004)

		MEDIA_VERSION(2000)