Commit 846297e1 authored by Marc Zyngier's avatar Marc Zyngier Committed by Thomas Gleixner
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irqchip/gic-v3-its: Handle non-coherent GICv4 redistributors 



Although the GICv3 code base has gained some handling of systems failing to
handle the shareability attributes, the GICv4 side of things has been
firmly ignored.

This is unfortunate, as the new recent addition of the "dma-noncoherent" is
supposed to apply to all of the GICR tables, and not just the ones that are
common to v3 and v4.

Add some checks to handle the VPROPBASE/VPENDBASE shareability and
cacheability attributes in the same way we deal with the other GICR_BASE
registers, wrapping the flag check in a helper for improved readability.

Note that this has been found by inspection only, as I don't have access to
HW that suffers from this particular issue.

Fixes: 3a0fff0f ("irqchip/gic-v3: Enable non-coherent redistributors/ITSes DT probing")
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Link: https://lore.kernel.org/r/20240213101206.2137483-2-maz@kernel.org
parent 8ad032cc

drivers/irqchip/irq-gic-v3-its.c

+25 −12
Original line number Diff line number Diff line
@@ -207,6 +207,11 @@ static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its) 
	return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);

}



static bool rdists_support_shareable(void)

{

	return !(gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE);

}



static u16 get_its_list(struct its_vm *vm)

{

	struct its_node *its;
@@ -2710,10 +2715,12 @@ static u64 inherit_vpe_l1_table_from_its(void) 
			break;

		}

		val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);

		if (rdists_support_shareable()) {

			val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,

					  FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));

			val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,

					  FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));

		}

		val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);



		return val;
@@ -2936,8 +2943,10 @@ static int allocate_vpe_l1_table(void) 
	WARN_ON(!IS_ALIGNED(pa, psz));



	val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);

	if (rdists_support_shareable()) {

		val |= GICR_VPROPBASER_RaWb;

		val |= GICR_VPROPBASER_InnerShareable;

	}

	val |= GICR_VPROPBASER_4_1_Z;

	val |= GICR_VPROPBASER_4_1_VALID;
@@ -3126,7 +3135,7 @@ static void its_cpu_init_lpis(void) 
	gicr_write_propbaser(val, rbase + GICR_PROPBASER);

	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);



	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)

	if (!rdists_support_shareable())

		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;



	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
@@ -3153,7 +3162,7 @@ static void its_cpu_init_lpis(void) 
	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);

	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);



	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)

	if (!rdists_support_shareable())

		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;



	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
@@ -3880,14 +3889,18 @@ static void its_vpe_schedule(struct its_vpe *vpe) 
	val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &

		GENMASK_ULL(51, 12);

	val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;

	if (rdists_support_shareable()) {

		val |= GICR_VPROPBASER_RaWb;

		val |= GICR_VPROPBASER_InnerShareable;

	}

	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);



	val  = virt_to_phys(page_address(vpe->vpt_page)) &

		GENMASK_ULL(51, 16);

	if (rdists_support_shareable()) {

		val |= GICR_VPENDBASER_RaWaWb;

		val |= GICR_VPENDBASER_InnerShareable;

	}

	/*

	 * There is no good way of finding out if the pending table is

	 * empty as we can race against the doorbell interrupt very