Commit 8488cdcb authored by Michael Ellerman's avatar Michael Ellerman
Browse files

powerpc/64s: Move dcbt/dcbtst sequence into a macro 



There's an almost identical code sequence to specify load/store access
hints in __copy_tofrom_user_power7(), copypage_power7() and
memcpy_power7().

Move the sequence into a common macro, which is passed the registers to
use as they differ slightly.

There also needs to be a copy in the selftests, it could be shared in
future if the headers are cleaned up / refactored.

Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20240229122521.762431-1-mpe@ellerman.id.au
parent d9cf600e

arch/powerpc/include/asm/ppc_asm.h

+12 −0
Original line number Diff line number Diff line
@@ -510,6 +510,18 @@ END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 
       lis     scratch,0x60000000@h;			\

       dcbt    0,scratch,0b01010



#define DCBT_SETUP_STREAMS(from, from_parms, to, to_parms, scratch)	\

	lis	scratch,0x8000;	/* GO=1 */				\

	clrldi	scratch,scratch,32;					\

	/* setup read stream 0 */					\

	dcbt	0,from,0b01000;		/* addr from */			\

	dcbt	0,from_parms,0b01010;	/* length and depth from */	\

	/* setup write stream 1 */					\

	dcbtst	0,to,0b01000;		/* addr to */			\

	dcbtst	0,to_parms,0b01010;	/* length and depth to */	\

	eieio;								\

	dcbt	0,scratch,0b01010;	/* all streams GO */



/*

 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them

 * keep the address intact to be compatible with code shared with

arch/powerpc/lib/copypage_power7.S

+1 −11
Original line number Diff line number Diff line
@@ -27,17 +27,7 @@ _GLOBAL(copypage_power7) 
#endif

	ori	r10,r7,1	/* stream=1 */



	lis	r8,0x8000	/* GO=1 */

	clrldi	r8,r8,32



	/* setup read stream 0  */

	dcbt	0,r4,0b01000  	/* addr from */

	dcbt	0,r7,0b01010   /* length and depth from */

	/* setup write stream 1 */

	dcbtst	0,r9,0b01000   /* addr to */

	dcbtst	0,r10,0b01010  /* length and depth to */

	eieio

	dcbt	0,r8,0b01010	/* all streams GO */

	DCBT_SETUP_STREAMS(r4, r7, r9, r10, r8)



#ifdef CONFIG_ALTIVEC

	mflr	r0

arch/powerpc/lib/copyuser_power7.S

+1 −11
Original line number Diff line number Diff line
@@ -298,17 +298,7 @@ err1; stb r0,0(r3) 
	or	r7,r7,r0

	ori	r10,r7,1	/* stream=1 */



	lis	r8,0x8000	/* GO=1 */

	clrldi	r8,r8,32



	/* setup read stream 0 */

	dcbt	0,r6,0b01000   /* addr from */

	dcbt	0,r7,0b01010   /* length and depth from */

	/* setup write stream 1 */

	dcbtst	0,r9,0b01000   /* addr to */

	dcbtst	0,r10,0b01010  /* length and depth to */

	eieio

	dcbt	0,r8,0b01010	/* all streams GO */

	DCBT_SETUP_STREAMS(r6, r7, r9, r10, r8)



	beq	cr1,.Lunwind_stack_nonvmx_copy

arch/powerpc/lib/memcpy_power7.S

+1 −9
Original line number Diff line number Diff line
@@ -244,15 +244,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 
	or	r7,r7,r0

	ori	r10,r7,1	/* stream=1 */



	lis	r8,0x8000	/* GO=1 */

	clrldi	r8,r8,32



	dcbt	0,r6,0b01000

	dcbt	0,r7,0b01010

	dcbtst	0,r9,0b01000

	dcbtst	0,r10,0b01010

	eieio

	dcbt	0,r8,0b01010	/* GO */

	DCBT_SETUP_STREAMS(r6, r7, r9, r10, r8)



	beq	cr1,.Lunwind_stack_nonvmx_copy

tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h

+12 −0
Original line number Diff line number Diff line
@@ -47,4 +47,16 @@ 
/* Default to taking the first of any alternative feature sections */

test_feature = 1



#define DCBT_SETUP_STREAMS(from, from_parms, to, to_parms, scratch)	\

	lis	scratch,0x8000;	/* GO=1 */				\

	clrldi	scratch,scratch,32;					\

	/* setup read stream 0 */					\

	dcbt	0,from,0b01000;		/* addr from */			\

	dcbt	0,from_parms,0b01010;	/* length and depth from */	\

	/* setup write stream 1 */					\

	dcbtst	0,to,0b01000;		/* addr to */			\

	dcbtst	0,to_parms,0b01010;	/* length and depth to */	\

	eieio;								\

	dcbt	0,scratch,0b01010;	/* all streams GO */



#endif /* __SELFTESTS_POWERPC_PPC_ASM_H */