Commit 84898f8e authored by Finley Xiao's avatar Finley Xiao Committed by Heiko Stuebner
Browse files

dt-bindings: clock: rockchip: Add RK3506 clock and reset unit 



Add device tree bindings for clock and reset unit on RK3506 SoC.
Add clock and reset IDs for RK3506 SoC.

Signed-off-by: default avatarFinley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251121075350.2564860-2-zhangqing@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 652c108c

Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3506 Clock and Reset Unit (CRU)



maintainers:

  - Finley Xiao <finley.xiao@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description:

  The RK3506 CRU generates the clock and also implements reset for SoC

  peripherals.



properties:

  compatible:

    const: rockchip,rk3506-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    maxItems: 1



  clock-names:

    const: xin



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    clock-controller@ff9a0000 {

      compatible = "rockchip,rk3506-cru";

      reg = <0xff9a0000 0x20000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      clocks = <&xin24m>;

      clock-names = "xin";

    };

include/dt-bindings/clock/rockchip,rk3506-cru.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.

 * Author: Finley Xiao <finley.xiao@rock-chips.com>

 */



#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H

#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H



/* cru plls */

#define PLL_GPLL			0

#define PLL_V0PLL			1

#define PLL_V1PLL			2



/* cru-clocks indices */

#define ARMCLK				3

#define CLK_DDR				4

#define XIN24M_GATE			5

#define CLK_GPLL_GATE			6

#define CLK_V0PLL_GATE			7

#define CLK_V1PLL_GATE			8

#define CLK_GPLL_DIV			9

#define CLK_GPLL_DIV_100M		10

#define CLK_V0PLL_DIV			11

#define CLK_V1PLL_DIV			12

#define CLK_INT_VOICE_MATRIX0		13

#define CLK_INT_VOICE_MATRIX1		14

#define CLK_INT_VOICE_MATRIX2		15

#define CLK_FRAC_UART_MATRIX0_MUX	16

#define CLK_FRAC_UART_MATRIX1_MUX	17

#define CLK_FRAC_VOICE_MATRIX0_MUX	18

#define CLK_FRAC_VOICE_MATRIX1_MUX	19

#define CLK_FRAC_COMMON_MATRIX0_MUX	20

#define CLK_FRAC_COMMON_MATRIX1_MUX	21

#define CLK_FRAC_COMMON_MATRIX2_MUX	22

#define CLK_FRAC_UART_MATRIX0		23

#define CLK_FRAC_UART_MATRIX1		24

#define CLK_FRAC_VOICE_MATRIX0		25

#define CLK_FRAC_VOICE_MATRIX1		26

#define CLK_FRAC_COMMON_MATRIX0		27

#define CLK_FRAC_COMMON_MATRIX1		28

#define CLK_FRAC_COMMON_MATRIX2		29

#define CLK_REF_USBPHY_TOP		30

#define CLK_REF_DPHY_TOP		31

#define ACLK_CORE_ROOT			32

#define PCLK_CORE_ROOT			33

#define PCLK_DBG			34

#define PCLK_CORE_GRF			35

#define PCLK_CORE_CRU			36

#define CLK_CORE_EMA_DETECT		37

#define CLK_REF_PVTPLL_CORE		38

#define PCLK_GPIO1			39

#define DBCLK_GPIO1			40

#define ACLK_CORE_PERI_ROOT		41

#define HCLK_CORE_PERI_ROOT		42

#define PCLK_CORE_PERI_ROOT		43

#define CLK_DSMC			44

#define ACLK_DSMC			45

#define PCLK_DSMC			46

#define CLK_FLEXBUS_TX			47

#define CLK_FLEXBUS_RX			48

#define ACLK_FLEXBUS			49

#define HCLK_FLEXBUS			50

#define ACLK_DSMC_SLV			51

#define HCLK_DSMC_SLV			52

#define ACLK_BUS_ROOT			53

#define HCLK_BUS_ROOT			54

#define PCLK_BUS_ROOT			55

#define ACLK_SYSRAM			56

#define HCLK_SYSRAM			57

#define ACLK_DMAC0			58

#define ACLK_DMAC1			59

#define HCLK_M0				60

#define PCLK_BUS_GRF			61

#define PCLK_TIMER			62

#define CLK_TIMER0_CH0			63

#define CLK_TIMER0_CH1			64

#define CLK_TIMER0_CH2			65

#define CLK_TIMER0_CH3			66

#define CLK_TIMER0_CH4			67

#define CLK_TIMER0_CH5			68

#define PCLK_WDT0			69

#define TCLK_WDT0			70

#define PCLK_WDT1			71

#define TCLK_WDT1			72

#define PCLK_MAILBOX			73

#define PCLK_INTMUX			74

#define PCLK_SPINLOCK			75

#define PCLK_DDRC			76

#define HCLK_DDRPHY			77

#define PCLK_DDRMON			78

#define CLK_DDRMON_OSC			79

#define PCLK_STDBY			80

#define HCLK_USBOTG0			81

#define HCLK_USBOTG0_PMU		82

#define CLK_USBOTG0_ADP			83

#define HCLK_USBOTG1			84

#define HCLK_USBOTG1_PMU		85

#define CLK_USBOTG1_ADP			86

#define PCLK_USBPHY			87

#define ACLK_DMA2DDR			88

#define PCLK_DMA2DDR			89

#define STCLK_M0			90

#define CLK_DDRPHY			91

#define CLK_DDRC_SRC			92

#define ACLK_DDRC_0			93

#define ACLK_DDRC_1			94

#define CLK_DDRC			95

#define CLK_DDRMON			96

#define HCLK_LSPERI_ROOT		97

#define PCLK_LSPERI_ROOT		98

#define PCLK_UART0			99

#define PCLK_UART1			100

#define PCLK_UART2			101

#define PCLK_UART3			102

#define PCLK_UART4			103

#define SCLK_UART0			104

#define SCLK_UART1			105

#define SCLK_UART2			106

#define SCLK_UART3			107

#define SCLK_UART4			108

#define PCLK_I2C0			109

#define CLK_I2C0			110

#define PCLK_I2C1			111

#define CLK_I2C1			112

#define PCLK_I2C2			113

#define CLK_I2C2			114

#define PCLK_PWM1			115

#define CLK_PWM1			116

#define CLK_OSC_PWM1			117

#define CLK_RC_PWM1			118

#define CLK_FREQ_PWM1			119

#define CLK_COUNTER_PWM1		120

#define PCLK_SPI0			121

#define CLK_SPI0			122

#define PCLK_SPI1			123

#define CLK_SPI1			124

#define PCLK_GPIO2			125

#define DBCLK_GPIO2			126

#define PCLK_GPIO3			127

#define DBCLK_GPIO3			128

#define PCLK_GPIO4			129

#define DBCLK_GPIO4			130

#define HCLK_CAN0			131

#define CLK_CAN0			132

#define HCLK_CAN1			133

#define CLK_CAN1			134

#define HCLK_PDM			135

#define MCLK_PDM			136

#define CLKOUT_PDM			137

#define MCLK_SPDIFTX			138

#define HCLK_SPDIFTX			139

#define HCLK_SPDIFRX			140

#define MCLK_SPDIFRX			141

#define MCLK_SAI0			142

#define HCLK_SAI0			143

#define MCLK_OUT_SAI0			144

#define MCLK_SAI1			145

#define HCLK_SAI1			146

#define MCLK_OUT_SAI1			147

#define HCLK_ASRC0			148

#define CLK_ASRC0			149

#define HCLK_ASRC1			150

#define CLK_ASRC1			151

#define PCLK_CRU			152

#define PCLK_PMU_ROOT			153

#define MCLK_ASRC0			154

#define MCLK_ASRC1			155

#define MCLK_ASRC2			156

#define MCLK_ASRC3			157

#define LRCK_ASRC0_SRC			158

#define LRCK_ASRC0_DST			159

#define LRCK_ASRC1_SRC			160

#define LRCK_ASRC1_DST			161

#define ACLK_HSPERI_ROOT		162

#define HCLK_HSPERI_ROOT		163

#define PCLK_HSPERI_ROOT		164

#define CCLK_SRC_SDMMC			165

#define HCLK_SDMMC			166

#define HCLK_FSPI			167

#define SCLK_FSPI			168

#define PCLK_SPI2			169

#define ACLK_MAC0			170

#define ACLK_MAC1			171

#define PCLK_MAC0			172

#define PCLK_MAC1			173

#define CLK_MAC_ROOT			174

#define CLK_MAC0			175

#define CLK_MAC1			176

#define MCLK_SAI2			177

#define HCLK_SAI2			178

#define MCLK_OUT_SAI2			179

#define MCLK_SAI3_SRC			180

#define HCLK_SAI3			181

#define MCLK_SAI3			182

#define MCLK_OUT_SAI3			183

#define MCLK_SAI4_SRC			184

#define HCLK_SAI4			185

#define MCLK_SAI4			186

#define HCLK_DSM			187

#define MCLK_DSM			188

#define PCLK_AUDIO_ADC			189

#define MCLK_AUDIO_ADC			190

#define MCLK_AUDIO_ADC_DIV4		191

#define PCLK_SARADC			192

#define CLK_SARADC			193

#define PCLK_OTPC_NS			194

#define CLK_SBPI_OTPC_NS		195

#define CLK_USER_OTPC_NS		196

#define PCLK_UART5			197

#define SCLK_UART5			198

#define PCLK_GPIO234_IOC		199

#define CLK_MAC_PTP_ROOT		200

#define CLK_MAC0_PTP			201

#define CLK_MAC1_PTP			202

#define CLK_SPI2			203

#define ACLK_VIO_ROOT			204

#define HCLK_VIO_ROOT			205

#define PCLK_VIO_ROOT			206

#define HCLK_RGA			207

#define ACLK_RGA			208

#define CLK_CORE_RGA			209

#define ACLK_VOP			210

#define HCLK_VOP			211

#define DCLK_VOP			212

#define PCLK_DPHY			213

#define PCLK_DSI_HOST			214

#define PCLK_TSADC			215

#define CLK_TSADC			216

#define CLK_TSADC_TSEN			217

#define PCLK_GPIO1_IOC			218

#define PCLK_OTPC_S			219

#define CLK_SBPI_OTPC_S			220

#define CLK_USER_OTPC_S			221

#define PCLK_OTP_MASK			222

#define PCLK_KEYREADER			223

#define HCLK_BOOTROM			224

#define PCLK_DDR_SERVICE		225

#define HCLK_CRYPTO_S			226

#define HCLK_KEYLAD			227

#define CLK_CORE_CRYPTO			228

#define CLK_PKA_CRYPTO			229

#define CLK_CORE_CRYPTO_S		230

#define CLK_PKA_CRYPTO_S		231

#define ACLK_CRYPTO_S			232

#define HCLK_RNG_S			233

#define CLK_CORE_CRYPTO_NS		234

#define CLK_PKA_CRYPTO_NS		235

#define ACLK_CRYPTO_NS			236

#define HCLK_CRYPTO_NS			237

#define HCLK_RNG			238

#define CLK_PMU				239

#define PCLK_PMU			240

#define CLK_PMU_32K			241

#define PCLK_PMU_CRU			242

#define PCLK_PMU_GRF			243

#define PCLK_GPIO0_IOC			244

#define PCLK_GPIO0			245

#define DBCLK_GPIO0			246

#define PCLK_GPIO1_SHADOW		247

#define DBCLK_GPIO1_SHADOW		248

#define PCLK_PMU_HP_TIMER		249

#define CLK_PMU_HP_TIMER		250

#define CLK_PMU_HP_TIMER_32K		251

#define PCLK_PWM0			252

#define CLK_PWM0			253

#define CLK_OSC_PWM0			254

#define CLK_RC_PWM0			255

#define CLK_MAC_OUT			256

#define CLK_REF_OUT0			257

#define CLK_REF_OUT1			258

#define CLK_32K_FRAC			259

#define CLK_32K_RC			260

#define CLK_32K				261

#define CLK_32K_PMU			262

#define PCLK_TOUCH_KEY			263

#define CLK_TOUCH_KEY			264

#define CLK_REF_PHY_PLL			265

#define CLK_REF_PHY_PMU_MUX		266

#define CLK_WIFI_OUT			267

#define CLK_V0PLL_REF			268

#define CLK_V1PLL_REF			269

#define CLK_32K_FRAC_MUX		270



#endif

include/dt-bindings/reset/rockchip,rk3506-cru.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.

 * Author: Finley Xiao <finley.xiao@rock-chips.com>

 */



#ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H

#define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H



/* CRU-->SOFTRST_CON00 */

#define SRST_NCOREPORESET0_AC	0

#define SRST_NCOREPORESET1_AC	1

#define SRST_NCOREPORESET2_AC	2

#define SRST_NCORESET0_AC	3

#define SRST_NCORESET1_AC	4

#define SRST_NCORESET2_AC	5

#define SRST_NL2RESET_AC	6

#define SRST_A_CORE_BIU_AC	7

#define SRST_H_M0_AC		8



/* CRU-->SOFTRST_CON02 */

#define SRST_NDBGRESET		9

#define SRST_P_CORE_BIU		10

#define SRST_PMU		11



/* CRU-->SOFTRST_CON03 */

#define SRST_P_DBG		12

#define SRST_POT_DBG		13

#define SRST_P_CORE_GRF		14

#define SRST_CORE_EMA_DETECT	15

#define SRST_REF_PVTPLL_CORE	16

#define SRST_P_GPIO1		17

#define SRST_DB_GPIO1		18



/* CRU-->SOFTRST_CON04 */

#define SRST_A_CORE_PERI_BIU	19

#define SRST_A_DSMC		20

#define SRST_P_DSMC		21

#define SRST_FLEXBUS		22

#define SRST_A_FLEXBUS		23

#define SRST_H_FLEXBUS		24

#define SRST_A_DSMC_SLV		25

#define SRST_H_DSMC_SLV		26

#define SRST_DSMC_SLV		27



/* CRU-->SOFTRST_CON05 */

#define SRST_A_BUS_BIU		28

#define SRST_H_BUS_BIU		29

#define SRST_P_BUS_BIU		30

#define SRST_A_SYSRAM		31

#define SRST_H_SYSRAM		32

#define SRST_A_DMAC0		33

#define SRST_A_DMAC1		34

#define SRST_H_M0		35

#define SRST_M0_JTAG		36

#define SRST_H_CRYPTO		37



/* CRU-->SOFTRST_CON06 */

#define SRST_H_RNG		38

#define SRST_P_BUS_GRF		39

#define SRST_P_TIMER0		40

#define SRST_TIMER0_CH0		41

#define SRST_TIMER0_CH1		42

#define SRST_TIMER0_CH2		43

#define SRST_TIMER0_CH3		44

#define SRST_TIMER0_CH4		45

#define SRST_TIMER0_CH5		46

#define SRST_P_WDT0		47

#define SRST_T_WDT0		48

#define SRST_P_WDT1		49

#define SRST_T_WDT1		50

#define SRST_P_MAILBOX		51

#define SRST_P_INTMUX		52

#define SRST_P_SPINLOCK		53



/* CRU-->SOFTRST_CON07 */

#define SRST_P_DDRC		54

#define SRST_H_DDRPHY		55

#define SRST_P_DDRMON		56

#define SRST_DDRMON_OSC		57

#define SRST_P_DDR_LPC		58

#define SRST_H_USBOTG0		59

#define SRST_USBOTG0_ADP	60

#define SRST_H_USBOTG1		61

#define SRST_USBOTG1_ADP	62

#define SRST_P_USBPHY		63

#define SRST_USBPHY_POR		64

#define SRST_USBPHY_OTG0	65

#define SRST_USBPHY_OTG1	66



/* CRU-->SOFTRST_CON08 */

#define SRST_A_DMA2DDR		67

#define SRST_P_DMA2DDR		68



/* CRU-->SOFTRST_CON09 */

#define SRST_USBOTG0_UTMI	69

#define SRST_USBOTG1_UTMI	70



/* CRU-->SOFTRST_CON10 */

#define SRST_A_DDRC_0		71

#define SRST_A_DDRC_1		72

#define SRST_A_DDR_BIU		73

#define SRST_DDRC		74

#define SRST_DDRMON		75



/* CRU-->SOFTRST_CON11 */

#define SRST_H_LSPERI_BIU	76

#define SRST_P_UART0		77

#define SRST_P_UART1		78

#define SRST_P_UART2		79

#define SRST_P_UART3		80

#define SRST_P_UART4		81

#define SRST_UART0		82

#define SRST_UART1		83

#define SRST_UART2		84

#define SRST_UART3		85

#define SRST_UART4		86

#define SRST_P_I2C0		87

#define SRST_I2C0		88



/* CRU-->SOFTRST_CON12 */

#define SRST_P_I2C1		89

#define SRST_I2C1		90

#define SRST_P_I2C2		91

#define SRST_I2C2		92

#define SRST_P_PWM1		93

#define SRST_PWM1		94

#define SRST_P_SPI0		95

#define SRST_SPI0		96

#define SRST_P_SPI1		97

#define SRST_SPI1		98

#define SRST_P_GPIO2		99

#define SRST_DB_GPIO2		100



/* CRU-->SOFTRST_CON13 */

#define SRST_P_GPIO3		101

#define SRST_DB_GPIO3		102

#define SRST_P_GPIO4		103

#define SRST_DB_GPIO4		104

#define SRST_H_CAN0		105

#define SRST_CAN0		106

#define SRST_H_CAN1		107

#define SRST_CAN1		108

#define SRST_H_PDM		109

#define SRST_M_PDM		110

#define SRST_PDM		111

#define SRST_SPDIFTX		112

#define SRST_H_SPDIFTX		113

#define SRST_H_SPDIFRX		114

#define SRST_SPDIFRX		115

#define SRST_M_SAI0		116



/* CRU-->SOFTRST_CON14 */

#define SRST_H_SAI0		117

#define SRST_M_SAI1		118

#define SRST_H_SAI1		119

#define SRST_H_ASRC0		120

#define SRST_ASRC0		121

#define SRST_H_ASRC1		122

#define SRST_ASRC1		123



/* CRU-->SOFTRST_CON17 */

#define SRST_H_HSPERI_BIU	124

#define SRST_H_SDMMC		125

#define SRST_H_FSPI		126

#define SRST_S_FSPI		127

#define SRST_P_SPI2		128

#define SRST_A_MAC0		129

#define SRST_A_MAC1		130



/* CRU-->SOFTRST_CON18 */

#define SRST_M_SAI2		131

#define SRST_H_SAI2		132

#define SRST_H_SAI3		133

#define SRST_M_SAI3		134

#define SRST_H_SAI4		135

#define SRST_M_SAI4		136

#define SRST_H_DSM		137

#define SRST_M_DSM		138

#define SRST_P_AUDIO_ADC	139

#define SRST_M_AUDIO_ADC	140



/* CRU-->SOFTRST_CON19 */

#define SRST_P_SARADC		141

#define SRST_SARADC		142

#define SRST_SARADC_PHY		143

#define SRST_P_OTPC_NS		144

#define SRST_SBPI_OTPC_NS	145

#define SRST_USER_OTPC_NS	146

#define SRST_P_UART5		147

#define SRST_UART5		148

#define SRST_P_GPIO234_IOC	149



/* CRU-->SOFTRST_CON21 */

#define SRST_A_VIO_BIU		150

#define SRST_H_VIO_BIU		151

#define SRST_H_RGA		152

#define SRST_A_RGA		153

#define SRST_CORE_RGA		154

#define SRST_A_VOP		155

#define SRST_H_VOP		156

#define SRST_VOP		157

#define SRST_P_DPHY		158

#define SRST_P_DSI_HOST		159

#define SRST_P_TSADC		160

#define SRST_TSADC		161



/* CRU-->SOFTRST_CON22 */

#define SRST_P_GPIO1_IOC	162



#endif