Commit 84985eb2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-fixes-for-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree fixes from Rob Herring:

 - Fix NIOS2 boot with external DTB

 - Add missing synchronization needed between fw_devlink and DT overlay
   removals

 - Fix some unit-address regex's to be hex only

 - Drop some 10+ year old "unstable binding" statements

 - Add new SoCs to QCom UFS binding

 - Add TPM bindings to TPM maintainers

* tag 'devicetree-fixes-for-6.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  nios2: Only use built-in devicetree blob if configured to do so
  dt-bindings: timer: narrow regex for unit address to hex numbers
  dt-bindings: soc: fsl: narrow regex for unit address to hex numbers
  dt-bindings: remoteproc: ti,davinci: remove unstable remark
  dt-bindings: clock: ti: remove unstable remark
  dt-bindings: clock: keystone: remove unstable remark
  of: module: prevent NULL pointer dereference in vsnprintf()
  dt-bindings: ufs: qcom: document SM6125 UFS
  dt-bindings: ufs: qcom: document SC7180 UFS
  dt-bindings: ufs: qcom: document SC8180X UFS
  of: dynamic: Synchronize of_changeset_destroy() with the devlink removals
  driver core: Introduce device_link_wait_removal()
  docs: dt-bindings: add missing address/size-cells to example
  MAINTAINERS: Add TPM DT bindings to TPM maintainers
parents af709adf de164a7f

Documentation/devicetree/bindings/clock/keystone-gate.txt

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Status: Unstable - ABI compatibility may be broken in the future



Binding for Keystone gate control driver which uses PSC controller IP.



This binding uses the common clock binding[1].

Documentation/devicetree/bindings/clock/keystone-pll.txt

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Status: Unstable - ABI compatibility may be broken in the future



Binding for keystone PLLs. The main PLL IP typically has a multiplier,

a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL

and PAPLL are controlled by the memory mapped register where as the Main

Documentation/devicetree/bindings/clock/ti/adpll.txt

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Binding for Texas Instruments ADPLL clock.



Binding status: Unstable - ABI compatibility may be broken in the future



This binding uses the common clock binding[1]. It assumes a

register-mapped ADPLL with two to three selectable input clocks

and three to four children.

Documentation/devicetree/bindings/clock/ti/apll.txt

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Binding for Texas Instruments APLL clock.



Binding status: Unstable - ABI compatibility may be broken in the future



This binding uses the common clock binding[1].  It assumes a

register-mapped APLL with usually two selectable input clocks

(reference clock and bypass clock), with analog phase locked

Documentation/devicetree/bindings/clock/ti/autoidle.txt

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Binding for Texas Instruments autoidle clock.



Binding status: Unstable - ABI compatibility may be broken in the future



This binding uses the common clock binding[1]. It assumes a register mapped

clock which can be put to idle automatically by hardware based on the usage

and a configuration bit setting. Autoidle clock is never an individual