Commit 84a357bb authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/ddi: Sanitize DDI_BUF_CTL register definitions 



Align the DDI_BUF_CTL register flag definitions with how this is done
elsewhere.

v2: Robustify macro calls with parens. (Jani)

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-12-imre.deak@intel.com
parent a2359283

drivers/gpu/drm/i915/i915_reg.h

+12 −10
Original line number Diff line number Diff line
@@ -3625,27 +3625,29 @@ enum skl_power_gate { 
#define _DDI_BUF_CTL_B				0x64100

/* Known as DDI_CTL_DE in MTL+ */

#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)

#define  DDI_BUF_CTL_ENABLE			(1 << 31)

#define  DDI_BUF_CTL_ENABLE			REG_BIT(31)

#define  XE2LPD_DDI_BUF_D2D_LINK_ENABLE		REG_BIT(29)

#define  XE2LPD_DDI_BUF_D2D_LINK_STATE		REG_BIT(28)

#define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)

#define  DDI_BUF_EMP_MASK			(0xf << 24)

#define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)

#define  DDI_BUF_EMP_MASK			REG_GENMASK(27, 24)

#define  DDI_BUF_TRANS_SELECT(n)		REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n))

#define  DDI_BUF_PHY_LINK_RATE_MASK		REG_GENMASK(23, 20)

#define  DDI_BUF_PHY_LINK_RATE(r)		REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r))

#define  DDI_BUF_PORT_DATA_MASK			REG_GENMASK(19, 18)

#define  DDI_BUF_PORT_DATA_10BIT		REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)

#define  DDI_BUF_PORT_DATA_20BIT		REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)

#define  DDI_BUF_PORT_DATA_40BIT		REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)

#define  DDI_BUF_PORT_REVERSAL			(1 << 16)

#define  DDI_BUF_PORT_REVERSAL			REG_BIT(16)

#define  DDI_BUF_LANE_STAGGER_DELAY_MASK	REG_GENMASK(15, 8)

#define  DDI_BUF_LANE_STAGGER_DELAY(symbols)	REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \

							       (symbols))

#define  DDI_BUF_IS_IDLE			(1 << 7)

#define  DDI_BUF_IS_IDLE			REG_BIT(7)

#define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)

#define  DDI_A_4_LANES				(1 << 4)

#define  DDI_PORT_WIDTH(width)			(((width) == 3 ? 4 : ((width) - 1)) << 1)

#define  DDI_PORT_WIDTH_MASK			(7 << 1)

#define  DDI_A_4_LANES				REG_BIT(4)

#define  DDI_PORT_WIDTH_MASK			REG_GENMASK(3, 1)

#define  DDI_PORT_WIDTH(width)			REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \

							       ((width) == 3 ? 4 : (width) - 1))

#define  DDI_PORT_WIDTH_SHIFT			1

#define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)

#define  DDI_INIT_DISPLAY_DETECTED		REG_BIT(0)



/* DDI Buffer Translations */

#define _DDI_BUF_TRANS_A		0x64E00