Commit 84aefafe authored by Randy Dunlap's avatar Randy Dunlap Committed by Stephen Boyd
Browse files

clk: linux/clk-provider.h: fix kernel-doc warnings and typos 



Fix spelling of "Structure".

Fix multiple kernel-doc warnings:

clk-provider.h:269: warning: Function parameter or member 'recalc_rate' not described in 'clk_ops'
clk-provider.h:468: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_with_accuracy_parent_data'
clk-provider.h:468: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_with_accuracy_parent_data'
clk-provider.h:482: warning: Function parameter or member 'parent_data' not described in 'clk_hw_register_fixed_rate_parent_accuracy'
clk-provider.h:482: warning: Excess function parameter 'parent_name' description in 'clk_hw_register_fixed_rate_parent_accuracy'
clk-provider.h:687: warning: Function parameter or member 'flags' not described in 'clk_divider'
clk-provider.h:1164: warning: Function parameter or member 'flags' not described in 'clk_fractional_divider'
clk-provider.h:1164: warning: Function parameter or member 'approximation' not described in 'clk_fractional_divider'
clk-provider.h:1213: warning: Function parameter or member 'flags' not described in 'clk_multiplier'

Fixes: 9fba738a ("clk: add duty cycle support")
Fixes: b2476490 ("clk: introduce the common clock framework")
Fixes: 2d34f09e ("clk: fixed-rate: Add support for specifying parents via DT/pointers")
Fixes: f5290d8e ("clk: asm9260: use parent index to link the reference clock")
Fixes: 9d9f78ed ("clk: basic clock hardware types")
Fixes: e2d0e90f ("clk: new basic clk type for fractional divider")
Fixes: f2e0a532 ("clk: Add a basic multiplier clock")

Signed-off-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/r/20230930221428.18463-1-rdunlap@infradead.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 0bb80ecc

include/linux/clk-provider.h

+8 −7
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ void clk_hw_forward_rate_request(const struct clk_hw *core, 
				 unsigned long parent_rate);



/**

 * struct clk_duty - Struture encoding the duty cycle ratio of a clock

 * struct clk_duty - Structure encoding the duty cycle ratio of a clock

 *

 * @num:	Numerator of the duty cycle ratio

 * @den:	Denominator of the duty cycle ratio
@@ -129,7 +129,7 @@ struct clk_duty { 
 * @restore_context: Restore the context of the clock after a restoration

 *		of power.

 *

 * @recalc_rate	Recalculate the rate of this clock, by querying hardware. The

 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The

 *		parent rate is an input parameter.  It is up to the caller to

 *		ensure that the prepare_mutex is held across this call. If the

 *		driver cannot figure out a rate for this clock, it must return
@@ -456,7 +456,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 
 * clock with the clock framework

 * @dev: device that is registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @parent_data: name of clock's parent

 * @flags: framework-specific flags

 * @fixed_rate: non-adjustable clock rate

 * @fixed_accuracy: non-adjustable clock accuracy
@@ -471,7 +471,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 
 * the clock framework

 * @dev: device that is registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @parent_data: name of clock's parent

 * @flags: framework-specific flags

 * @fixed_rate: non-adjustable clock rate

 */
@@ -649,7 +649,7 @@ struct clk_div_table { 
 * Clock with an adjustable divider affecting its output frequency.  Implements

 * .recalc_rate, .set_rate and .round_rate

 *

 * Flags:

 * @flags:

 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the

 *	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is

 *	the raw value read from the register, with the value of zero considered
@@ -1130,11 +1130,12 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, 
 * @mwidth:	width of the numerator bit field

 * @nshift:	shift to the denominator bit field

 * @nwidth:	width of the denominator bit field

 * @approximation: clk driver's callback for calculating the divider clock

 * @lock:	register lock

 *

 * Clock with adjustable fractional divider affecting its output frequency.

 *

 * Flags:

 * @flags:

 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator

 *	is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED

 *	is set then the numerator and denominator are both the value read
@@ -1191,7 +1192,7 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 
 * Clock with an adjustable multiplier affecting its output frequency.

 * Implements .recalc_rate, .set_rate and .round_rate

 *

 * Flags:

 * @flags:

 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read

 *	from the register, with 0 being a valid value effectively

 *	zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is