Commit 84b25926 authored by Dave Jiang's avatar Dave Jiang
Browse files

acpi: numa: Add support to enumerate and store extended linear address mode 

Store the address mode as part of the cache attriutes. Export the mode
attribute to sysfs as all other cache attributes.

Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/


Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarLi Ming <ming.li@zohomail.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250226162224.3633792-2-dave.jiang@intel.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 2014c95a

Documentation/ABI/stable/sysfs-devices-node

+6 −0
Original line number Diff line number Diff line
@@ -177,6 +177,12 @@ Description: 
		The cache write policy: 0 for write-back, 1 for write-through,

		other or unknown.



What:		/sys/devices/system/node/nodeX/memory_side_cache/indexY/address_mode

Date:		March 2025

Contact:	Dave Jiang <dave.jiang@intel.com>

Description:

		The address mode: 0 for reserved, 1 for extended-linear.



What:		/sys/devices/system/node/nodeX/x86/sgx_total_bytes

Date:		November 2021

Contact:	Jarkko Sakkinen <jarkko@kernel.org>

drivers/acpi/numa/hmat.c

+5 −0
Original line number Diff line number Diff line
@@ -506,6 +506,11 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, 
	switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) {

	case ACPI_HMAT_CA_DIRECT_MAPPED:

		tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP;

		/* Extended Linear mode is only valid if cache is direct mapped */

		if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) {

			tcache->cache_attrs.address_mode =

				NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR;

		}

		break;

	case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING:

		tcache->cache_attrs.indexing = NODE_CACHE_INDEXED;

drivers/base/node.c

+2 −0
Original line number Diff line number Diff line
@@ -244,12 +244,14 @@ CACHE_ATTR(size, "%llu") 
CACHE_ATTR(line_size, "%u")

CACHE_ATTR(indexing, "%u")

CACHE_ATTR(write_policy, "%u")

CACHE_ATTR(address_mode, "%#x")



static struct attribute *cache_attrs[] = {

	&dev_attr_indexing.attr,

	&dev_attr_size.attr,

	&dev_attr_line_size.attr,

	&dev_attr_write_policy.attr,

	&dev_attr_address_mode.attr,

	NULL,

};

ATTRIBUTE_GROUPS(cache);

include/linux/node.h

+7 −0
Original line number Diff line number Diff line
@@ -57,6 +57,11 @@ enum cache_write_policy { 
	NODE_CACHE_WRITE_OTHER,

};



enum cache_mode {

	NODE_CACHE_ADDR_MODE_RESERVED,

	NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR,

};



/**

 * struct node_cache_attrs - system memory caching attributes

 *
@@ -65,6 +70,7 @@ enum cache_write_policy { 
 * @size:		Total size of cache in bytes

 * @line_size:		Number of bytes fetched on a cache miss

 * @level:		The cache hierarchy level

 * @address_mode:		The address mode

 */

struct node_cache_attrs {

	enum cache_indexing indexing;
@@ -72,6 +78,7 @@ struct node_cache_attrs { 
	u64 size;

	u16 line_size;

	u8 level;

	u16 address_mode;

};



#ifdef CONFIG_HMEM_REPORTING