Commit 84b6f850 authored by Shuicheng Lin's avatar Shuicheng Lin Committed by Lucas De Marchi
Browse files

drm/xe: Use xe_mmio_read32() to read mtcfg register 



The mtcfg register is a 32-bit register and should therefore be
accessed using xe_mmio_read32().

Other 3 changes per codestyle suggestion:
"
xe_mmio.c:83: CHECK: Alignment should match open parenthesis
xe_mmio.c:131: CHECK: Comparison to NULL could be written "!xe->mmio.regs"
xe_mmio.c:315: CHECK: line length of 103 exceeds 100 columns
"

Fixes: dd08ebf6 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Reviewed-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarShuicheng Lin <shuicheng.lin@intel.com>
Link: https://lore.kernel.org/r/20250513153010.3464767-1-shuicheng.lin@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
(cherry picked from commit d2662cf8)
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 57b34cba

drivers/gpu/drm/xe/xe_mmio.c

+5 −5
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static void mmio_multi_tile_setup(struct xe_device *xe, size_t tile_mmio_size) 
		 * is fine as it's going to the root tile's mmio, that's

		 * guaranteed to be initialized earlier in xe_mmio_probe_early()

		 */

		mtcfg = xe_mmio_read64_2x32(mmio, XEHP_MTCFG_ADDR);

		mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);

		tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;



		if (tile_count < xe->info.tile_count) {
@@ -128,7 +128,7 @@ int xe_mmio_probe_early(struct xe_device *xe) 
	 */

	xe->mmio.size = pci_resource_len(pdev, GTTMMADR_BAR);

	xe->mmio.regs = pci_iomap(pdev, GTTMMADR_BAR, 0);

	if (xe->mmio.regs == NULL) {

	if (!xe->mmio.regs) {

		drm_err(&xe->drm, "failed to map registers\n");

		return -EIO;

	}
@@ -309,8 +309,8 @@ u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg) 
	return (u64)udw << 32 | ldw;

}



static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,

			    u32 *out_val, bool atomic, bool expect_match)

static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,

			    u32 timeout_us, u32 *out_val, bool atomic, bool expect_match)

{

	ktime_t cur = ktime_get_raw();

	const ktime_t end = ktime_add_us(cur, timeout_us);