Commit 851faa88 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2025-02-01' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "This is only AMD fixes:

  amdgpu:
   - GC 12 fix
   - Aldebaran fix
   - DCN 3.5 fix
   - Freesync fix

  amdkfd:
   - Per queue reset fix
   - MES fix"

* tag 'drm-next-2025-02-01' of https://gitlab.freedesktop.org/drm/kernel:
  drm/amd/display: restore invalid MSA timing check for freesync
  drm/amdkfd: only flush the validate MES contex
  drm/amd/display: Correct register address in dcn35
  drm/amd/pm: Mark MM activity as unsupported
  drm/amd/amdgpu: change the config of cgcg on gfx12
  drm/amdkfd: Block per-queue reset when halt_if_hws_hang=1
parents 0c0746f9 8dcb26b4

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+0 −11
Original line number Diff line number Diff line
@@ -4021,17 +4021,6 @@ static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade 


		if (def != data)

			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);



		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);

		data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;

		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);



		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */

		if (adev->sdma.num_instances > 1) {

			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

			data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;

			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);

		}

	}

}

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

+2 −2
Original line number Diff line number Diff line
@@ -2325,9 +2325,9 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, 
	 */

	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];

	if (mqd_mgr->check_preemption_failed(mqd_mgr, dqm->packet_mgr.priv_queue->queue->mqd)) {

		if (reset_queues_on_hws_hang(dqm)) {

		while (halt_if_hws_hang)

			schedule();

		if (reset_queues_on_hws_hang(dqm)) {

			dqm->is_hws_hang = true;

			kfd_hws_hang(dqm);

			retval = -ETIME;

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

+5 −2
Original line number Diff line number Diff line
@@ -86,9 +86,12 @@ void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 


	if (pdd->already_dequeued)

		return;



	/* The MES context flush needs to filter out the case which the

	 * KFD process is created without setting up the MES context and

	 * queue for creating a compute queue.

	 */

	dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd);

	if (dev->kfd->shared_resources.enable_mes &&

	if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr &&

	    down_read_trylock(&dev->adev->reset_domain->sem)) {

		amdgpu_mes_flush_shader_debugger(dev->adev,

						 pdd->proc_ctx_gpu_addr);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+8 −4
Original line number Diff line number Diff line
@@ -12326,10 +12326,14 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 


	if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||

		     sink->sink_signal == SIGNAL_TYPE_EDP)) {

		if (amdgpu_dm_connector->dc_link &&

		    amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {

			amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;

			amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;

			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)

				freesync_capable = true;

		}



		parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);



		if (vsdb_info.replay_mode) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ 
#define mmCLK1_CLK4_ALLOW_DS 0x16EA8

#define mmCLK1_CLK5_ALLOW_DS 0x16EB1



#define mmCLK5_spll_field_8 0x1B04B

#define mmCLK5_spll_field_8 0x1B24B

#define mmDENTIST_DISPCLK_CNTL 0x0124

#define regDENTIST_DISPCLK_CNTL 0x0064

#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1