Commit 855e9d0f authored by Neil Armstrong's avatar Neil Armstrong Committed by Rob Clark
Browse files

drm/msm: adreno: enable GMU bandwidth for A740 and A750 



Now all the DDR bandwidth voting via the GPU Management Unit (GMU)
is in place, declare the Bus Control Modules (BCMs) and the
corresponding parameters in the GPU info struct.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAkhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/629401/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 7047e655

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

+22 −0
Original line number Diff line number Diff line
@@ -1388,6 +1388,17 @@ static const struct adreno_info a7xx_gpus[] = { 
			.pwrup_reglist = &a7xx_pwrup_reglist,

			.gmu_chipid = 0x7020100,

			.gmu_cgc_mode = 0x00020202,

			.bcms = (const struct a6xx_bcm[]) {

				{ .name = "SH0", .buswidth = 16 },

				{ .name = "MC0", .buswidth = 4 },

				{

					.name = "ACV",

					.fixed = true,

					.perfmode = BIT(3),

					.perfmode_bw = 16500000,

				},

				{ /* sentinel */ },

			},

		},

		.address_space_size = SZ_16G,

		.preempt_record_size = 4192 * SZ_1K,
@@ -1432,6 +1443,17 @@ static const struct adreno_info a7xx_gpus[] = { 
			.pwrup_reglist = &a7xx_pwrup_reglist,

			.gmu_chipid = 0x7090100,

			.gmu_cgc_mode = 0x00020202,

			.bcms = (const struct a6xx_bcm[]) {

				{ .name = "SH0", .buswidth = 16 },

				{ .name = "MC0", .buswidth = 4 },

				{

					.name = "ACV",

					.fixed = true,

					.perfmode = BIT(2),

					.perfmode_bw = 10687500,

				},

				{ /* sentinel */ },

			},

		},

		.address_space_size = SZ_16G,

		.preempt_record_size = 3572 * SZ_1K,