Commit 8582976a authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull phy updates from Vinod Koul:
 "New Support:

   - Qualcomm Milos Synopsys eUSB2 PHY, SM8750 QMP phy support, M31
     eUSB2 PHY driver

   - Samsung Exynos990 usbdrd phy, Exynos7870 MIPI phy support

   - Renesas RZ/V2N usb2-phy support

  Updates:

   - Bulk Yaml binding conversion By Rob H (too many to be listed)

   - cadence: Sierra PCIe, USB PHY multilink configuration support

   - Qualcomm refactoring of UFS PHY reset and UFS driver support for
     phy calibrate API"

* tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (74 commits)
  phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
  dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema
  dt-bindings: phy: Convert ti,da830-usb-phy to DT schema
  dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example
  dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
  phy: exynos-mipi-video: correct cam0 sysreg property name for exynos7870
  phy: qcom: phy-qcom-snps-eusb2: Update init sequence per HPG 1.0.2
  phy: qcom: phy-qcom-snps-eusb2: Add missing write from init sequence
  dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY
  dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible
  phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal
  phy: rockchip-pcie: Enable all four lanes if required
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
  phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750
  phy: qcom: m31-eusb2: drop registration printk
  phy: qcom: m31-eusb2: fix match data santity check
  phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P
  phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registers
  dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values
  phy: mediatek: tphy: Cleanup and document slew calibration
  ...
parents 7a64bdfa 4a3556b8
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@@ -19,7 +19,7 @@ which are described in the following files:
- Documentation/devicetree/bindings/power/supply/cpcap-battery.yaml
- Documentation/devicetree/bindings/power/supply/cpcap-charger.yaml
- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt
- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
- Documentation/devicetree/bindings/phy/motorola,cpcap-usb-phy.yaml
- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
- Documentation/devicetree/bindings/rtc/cpcap-rtc.txt
- Documentation/devicetree/bindings/leds/leds-cpcap.txt
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/apm,xgene-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: APM X-Gene 15Gbps Multi-purpose PHY

maintainers:
  - Khuong Dinh <khuong@os.amperecomputing.com>

description:
  PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
  PHY (pair of lanes) has its own node.

properties:
  compatible:
    items:
      - const: apm,xgene-phy

  reg:
    maxItems: 1

  '#phy-cells':
    description:
      Possible values are 0 (SATA), 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
    const: 1

  clocks:
    maxItems: 1

  apm,tx-eye-tuning:
    description:
      Manual control to fine tune the capture of the serial bit lines from the
      automatic calibrated position. Two set of 3-tuple setting for each
      supported link speed on the host. Range from 0 to 127 in unit of one bit
      period.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 2
    maxItems: 2
    items:
      minItems: 3
      maxItems: 3
      items:
        minimum: 0
        maximum: 127
        default: 10

  apm,tx-eye-direction:
    description:
      Eye tuning manual control direction. 0 means sample data earlier than the
      nominal sampling point. 1 means sample data later than the nominal
      sampling point. Two set of 3-tuple setting for each supported link speed
      on the host.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 2
    maxItems: 2
    items:
      minItems: 3
      maxItems: 3
      items:
        enum: [0, 1]
        default: 0

  apm,tx-boost-gain:
    description:
      Frequency boost AC (LSB 3-bit) and DC (2-bit) gain control. Two set of
      3-tuple setting for each supported link speed on the host. Range is
      between 0 to 31 in unit of dB. Default is 3.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 2
    maxItems: 2
    items:
      minItems: 3
      maxItems: 3
      items:
        minimum: 0
        maximum: 31

  apm,tx-amplitude:
    description:
      Amplitude control. Two set of 3-tuple setting for each supported link
      speed on the host. Range is between 0 to 199500 in unit of uV.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 2
    maxItems: 2
    items:
      minItems: 3
      maxItems: 3
      items:
        minimum: 0
        maximum: 199500
        default: 199500

  apm,tx-pre-cursor1:
    description:
      1st pre-cursor emphasis taps control. Two set of 3-tuple setting for
      each supported link speed on the host. Range is 0 to 273000 in unit of
      uV.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 2
    maxItems: 2
    items:
      minItems: 3
      maxItems: 3
      items:
        minimum: 0
        maximum: 273000
        default: 0

  apm,tx-pre-cursor2:
    description:
      2nd pre-cursor emphasis taps control. Two set of 3-tuple setting for
      each supported link speed on the host. Range is 0 to 127400 in unit uV.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 2
    maxItems: 2
    items:
      minItems: 3
      maxItems: 3
      items:
        minimum: 0
        maximum: 127400
        default: 0

  apm,tx-post-cursor:
    description: |
      Post-cursor emphasis taps control. Two set of 3-tuple setting for Gen1,
      Gen2, and Gen3 link speeds. Range is between 0 to 31 in unit of 18.2mV.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 2
    maxItems: 2
    items:
      minItems: 3
      maxItems: 3
      items:
        minimum: 0
        maximum: 31
        default: 0xf

  apm,tx-speed:
    description: >
      Tx operating speed. One set of 3-tuple for each supported link speed on
      the host:

        0 = 1-2Gbps
        1 = 2-4Gbps (1st tuple default)
        2 = 4-8Gbps
        3 = 8-15Gbps (2nd tuple default)
        4 = 2.5-4Gbps
        5 = 4-5Gbps
        6 = 5-6Gbps
        7 = 6-16Gbps (3rd tuple default).

    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 3
    maxItems: 3
    items:
      maximum: 7

additionalProperties: false

examples:
  - |
    phy@1f21a000 {
        compatible = "apm,xgene-phy";
        reg = <0x1f21a000 0x100>;
        #phy-cells = <1>;
    };
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* APM X-Gene 15Gbps Multi-purpose PHY nodes

PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
PHY (pair of lanes) has its own node.

Required properties:
- compatible		: Shall be "apm,xgene-phy".
- reg			: PHY memory resource is the SDS PHY access resource.
- #phy-cells		: Shall be 1 as it expects one argument for setting
			  the mode of the PHY. Possible values are 0 (SATA),
			  1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).

Optional properties:
- status		: Shall be "ok" if enabled or "disabled" if disabled.
			  Default is "ok".
- clocks		: Reference to the clock entry.
- apm,tx-eye-tuning	: Manual control to fine tune the capture of the serial
			  bit lines from the automatic calibrated position.
			  Two set of 3-tuple setting for each (up to 3)
			  supported link speed on the host. Range from 0 to
			  127 in unit of one bit period. Default is 10.
- apm,tx-eye-direction	: Eye tuning manual control direction. 0 means sample
			  data earlier than the nominal sampling point. 1 means
			  sample data later than the nominal sampling point.
			  Two set of 3-tuple setting for each (up to 3)
			  supported link speed on the host. Default is 0.
- apm,tx-boost-gain	: Frequency boost AC (LSB 3-bit) and DC (2-bit)
			  gain control. Two set of 3-tuple setting for each
			  (up to 3) supported link speed on the host. Range is
			  between 0 to 31 in unit of dB. Default is 3.
- apm,tx-amplitude	: Amplitude control. Two set of 3-tuple setting for
			  each (up to 3) supported link speed on the host.
			  Range is between 0 to 199500 in unit of uV.
			  Default is 199500 uV.
- apm,tx-pre-cursor1	: 1st pre-cursor emphasis taps control. Two set of
			  3-tuple setting for each (up to 3) supported link
			  speed on the host. Range is 0 to 273000 in unit of
			  uV. Default is 0.
- apm,tx-pre-cursor2	: 2nd pre-cursor emphasis taps control. Two set of
			  3-tuple setting for each (up to 3) supported link
			  speed on the host. Range is 0 to 127400 in unit uV.
			  Default is 0x0.
- apm,tx-post-cursor	: Post-cursor emphasis taps control. Two set of
			  3-tuple setting for Gen1, Gen2, and Gen3. Range is
			  between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
- apm,tx-speed		: Tx operating speed. One set of 3-tuple for each
			  supported link speed on the host.
			   0 = 1-2Gbps
			   1 = 2-4Gbps (1st tuple default)
			   2 = 4-8Gbps
			   3 = 8-15Gbps (2nd tuple default)
			   4 = 2.5-4Gbps
			   5 = 4-5Gbps
			   6 = 5-6Gbps
			   7 = 6-16Gbps (3rd tuple default)

NOTE: PHY override parameters are board specific setting.

Example:
		phy1: phy@1f21a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f21a000 0x0 0x100>;
			#phy-cells = <1>;
		};

		phy2: phy@1f22a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f22a000 0x0 0x100>;
			#phy-cells = <1>;
		};

		phy3: phy@1f23a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f23a000 0x0 0x100>;
			#phy-cells = <1>;
		};
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Berlin SATA PHY
---------------

Required properties:
- compatible: should be one of
    "marvell,berlin2-sata-phy"
    "marvell,berlin2q-sata-phy"
- address-cells: should be 1
- size-cells: should be 0
- phy-cells: from the generic PHY bindings, must be 1
- reg: address and length of the register
- clocks: reference to the clock entry

Sub-nodes:
Each PHY should be represented as a sub-node.

Sub-nodes required properties:
- reg: the PHY number

Example:
	sata_phy: phy@f7e900a0 {
		compatible = "marvell,berlin2q-sata-phy";
		reg = <0xf7e900a0 0x200>;
		clocks = <&chip CLKID_SATA>;
		#address-cells = <1>;
		#size-cells = <0>;
		#phy-cells = <1>;

		sata-phy@0 {
			reg = <0>;
		};

		sata-phy@1 {
			reg = <1>;
		};
	};
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* Marvell Berlin USB PHY

Required properties:
- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
- reg: base address and length of the registers
- #phys-cells: should be 0
- resets: reference to the reset controller

Example:

	usb-phy@f774000 {
		compatible = "marvell,berlin2-usb-phy";
		reg = <0xf774000 0x128>;
		#phy-cells = <0>;
		resets = <&chip 0x104 14>;
	};
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