Commit 858fbd72 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/c1-pro-erratum-4193714' into for-next/core 

* for-next/c1-pro-erratum-4193714:
  : Work around C1-Pro erratum 4193714 (CVE-2026-0995)
  arm64: errata: Work around early CME DVMSync acknowledgement
  arm64: cputype: Add C1-Pro definitions
  arm64: tlb: Pass the corresponding mm to __tlbi_sync_s1ish()
  arm64: tlb: Introduce __tlbi_sync_s1ish_{kernel,batch}() for TLB maintenance
parents 818f644e 0baba94a

Documentation/arch/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -202,6 +202,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3AE   | #3312417        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | C1-Pro          | #4193714        | ARM64_ERRATUM_4193714       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | ARM_SMMU_MMU_500_CPRE_ERRATA|

|                |                 | #562869,1047329 |                             |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -1149,6 +1149,18 @@ config ARM64_ERRATUM_4311569 


	  If unsure, say Y.



config ARM64_ERRATUM_4193714

	bool "C1-Pro: 4193714: SME DVMSync early acknowledgement"

	depends on ARM64_SME

	default y

	help

	  Enable workaround for C1-Pro acknowledging the DVMSync before

	  the SME memory accesses are complete. This will cause TLB

	  maintenance for processes using SME to also issue an IPI to

	  the affected CPUs.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cpucaps.h

+2 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ cpucap_is_possible(const unsigned int cap) 
		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI);

	case ARM64_WORKAROUND_SPECULATIVE_SSBS:

		return IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386);

	case ARM64_WORKAROUND_4193714:

		return IS_ENABLED(CONFIG_ARM64_ERRATUM_4193714);

	case ARM64_MPAM:

		/*

		 * KVM MPAM support doesn't rely on the host kernel supporting MPAM.

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ 
#define ARM_CPU_PART_CORTEX_A725	0xD87

#define ARM_CPU_PART_CORTEX_A720AE	0xD89

#define ARM_CPU_PART_NEOVERSE_N3	0xD8E

#define ARM_CPU_PART_C1_PRO		0xD8B



#define APM_CPU_PART_XGENE		0x000

#define APM_CPU_VAR_POTENZA		0x00
@@ -189,6 +190,7 @@ 
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)

#define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)

#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)

#define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

arch/arm64/include/asm/fpsimd.h

+21 −0
Original line number Diff line number Diff line
@@ -428,6 +428,24 @@ static inline size_t sme_state_size(struct task_struct const *task) 
	return __sme_state_size(task_get_sme_vl(task));

}



void sme_enable_dvmsync(void);

void sme_set_active(void);

void sme_clear_active(void);



static inline void sme_enter_from_user_mode(void)

{

	if (alternative_has_cap_unlikely(ARM64_WORKAROUND_4193714) &&

	    test_thread_flag(TIF_SME))

		sme_clear_active();

}



static inline void sme_exit_to_user_mode(void)

{

	if (alternative_has_cap_unlikely(ARM64_WORKAROUND_4193714) &&

	    test_thread_flag(TIF_SME))

		sme_set_active();

}



#else



static inline void sme_user_disable(void) { BUILD_BUG(); }
@@ -456,6 +474,9 @@ static inline size_t sme_state_size(struct task_struct const *task) 
	return 0;

}



static inline void sme_enter_from_user_mode(void) { }

static inline void sme_exit_to_user_mode(void) { }



#endif /* ! CONFIG_ARM64_SME */



/* For use by EFI runtime services calls only */