Commit 85c2601e authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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arm64: dts: renesas: r8a78000: Fix out-of-range SPI interrupt numbers 



SPI interrupts are in the range 0-987.  Extended SPI interrupts should
use GIC_ESPI, instead of abusing GIC_SPI with a manual offset of 4064.

Fixes: 63500d12 ("arm64: dts: renesas: Add R8A78000 SoC support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/1f9dd274720ea1b66617a5dd84f76c3efc829dc8.1772641415.git.geert+renesas@glider.be
parent 6dcbb6f0

arch/arm64/boot/dts/renesas/r8a78000.dtsi

+8 −8
Original line number Diff line number Diff line
@@ -698,7 +698,7 @@ scif0: serial@c0700000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0700000 0 0x40>;

			interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -708,7 +708,7 @@ scif1: serial@c0704000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0704000 0 0x40>;

			interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -718,7 +718,7 @@ scif3: serial@c0708000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0708000 0 0x40>;

			interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -728,7 +728,7 @@ scif4: serial@c070c000 { 
			compatible = "renesas,scif-r8a78000",

				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc070c000 0 0x40>;

			interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -738,7 +738,7 @@ hscif0: serial@c0710000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0710000 0 0x60>;

			interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -748,7 +748,7 @@ hscif1: serial@c0714000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0714000 0 0x60>;

			interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -758,7 +758,7 @@ hscif2: serial@c0718000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc0718000 0 0x60>;

			interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";
@@ -768,7 +768,7 @@ hscif3: serial@c071c000 { 
			compatible = "renesas,hscif-r8a78000",

				     "renesas,rcar-gen5-hscif", "renesas,hscif";

			reg = <0 0xc071c000 0 0x60>;

			interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";