Commit 85c43540 authored by Keguang Zhang's avatar Keguang Zhang Committed by Thomas Bogendoerfer
Browse files

MIPS: loongson32: Switch to generic core 

The generic MIPS core is fully compatible with Loongson-1 SoCs,
so migrate Loongson-1 to it.

Main changes are:
 - Merge CPU_LOONGSON1B and CPU_LOONGSON1C into a unified CPU_LOONGSON32,
   as both are based on the GS232 core.
 - Consolidate LOONGSON1_LS1B and LOONGSON1_LS1C Kconfig options into
   MACH_LOONGSON32.
 - Enable MACH_GENERIC_CORE and remove the legacy custom implementation.
 - Remove all Loongson-1 platform devices and associated code,
   which are now obsolete due to Device Tree support.
 - Misc cleanup.

Partially based on earlier work by Jiaxun Yang.

Link: https://lore.kernel.org/all/20190411121915.8040-4-jiaxun.yang@flygoat.com/


Signed-off-by: default avatarKeguang Zhang <keguang.zhang@gmail.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent ec7c2a10

MAINTAINERS

+0 −1
Original line number Diff line number Diff line
@@ -17017,7 +17017,6 @@ L: linux-mips@vger.kernel.org 
S:	Maintained

F:	Documentation/devicetree/bindings/*/loongson,ls1*.yaml

F:	arch/mips/boot/dts/loongson/loongson1*

F:	arch/mips/include/asm/mach-loongson32/

F:	arch/mips/loongson32/

F:	drivers/*/*loongson1*

F:	drivers/mtd/nand/raw/loongson1-nand-controller.c

arch/mips/Kconfig

+32 −32
Original line number Diff line number Diff line
@@ -480,6 +480,23 @@ config LANTIQ 


config MACH_LOONGSON32

	bool "Loongson 32-bit family of machines"

	select MACH_GENERIC_CORE

	select USE_OF

	select BUILTIN_DTB

	select BOOT_ELF32

	select CEVT_R4K

	select CSRC_R4K

	select COMMON_CLK

	select DMA_NONCOHERENT

	select GENERIC_IRQ_SHOW_LEVEL

	select IRQ_MIPS_CPU

	select LS1X_IRQ

	select SYS_HAS_CPU_LOONGSON32

	select SYS_HAS_EARLY_PRINTK

	select USE_GENERIC_EARLY_PRINTK_8250

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select SYS_SUPPORTS_ZBOOT

	help

	  This enables support for the Loongson-1 family of machines.
@@ -1386,25 +1403,20 @@ config CPU_LOONGSON2F 
	  have a similar programming interface with FPGA northbridge used in

	  Loongson2E.



config CPU_LOONGSON1B

	bool "Loongson 1B"

	depends on SYS_HAS_CPU_LOONGSON1B

	select CPU_LOONGSON32

	select LEDS_GPIO_REGISTER

	help

	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32

	  Release 1 instruction set and part of the MIPS32 Release 2

	  instruction set.



config CPU_LOONGSON1C

	bool "Loongson 1C"

	depends on SYS_HAS_CPU_LOONGSON1C

	select CPU_LOONGSON32

config CPU_LOONGSON32

	bool "Loongson 32-bit CPU"

	depends on SYS_HAS_CPU_LOONGSON32

	select CPU_MIPS32

	select CPU_MIPSR2

	select CPU_HAS_PREFETCH

	select CPU_HAS_LOAD_STORE_LR

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_CPUFREQ

	select LEDS_GPIO_REGISTER

	help

	  The Loongson 1C is a 32-bit SoC, which implements the MIPS32

	  Release 1 instruction set and part of the MIPS32 Release 2

	  instruction set.

	  The Loongson GS232 microarchitecture implements the MIPS32 Release 1

	  instruction set and part of the MIPS32 Release 2 instruction set.



config CPU_MIPS32_R1

	bool "MIPS32 Release 1"
@@ -1839,15 +1851,6 @@ config CPU_LOONGSON2EF 
	select CPU_SUPPORTS_HUGEPAGES

	select RTC_MC146818_LIB



config CPU_LOONGSON32

	bool

	select CPU_MIPS32

	select CPU_MIPSR2

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_CPUFREQ



config CPU_BMIPS32_3300

	select SMP_UP if SMP

	bool
@@ -1885,10 +1888,7 @@ config SYS_HAS_CPU_LOONGSON2F 
	select CPU_SUPPORTS_CPUFREQ

	select CPU_SUPPORTS_ADDRWINCFG if 64BIT



config SYS_HAS_CPU_LOONGSON1B

	bool



config SYS_HAS_CPU_LOONGSON1C

config SYS_HAS_CPU_LOONGSON32

	bool



config SYS_HAS_CPU_MIPS32_R1
@@ -2999,8 +2999,8 @@ choice 
	prompt "Kernel command line type"

	depends on !CMDLINE_OVERRIDE

	default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \

					 !MACH_LOONGSON64 && !MIPS_MALTA && \

					 !CAVIUM_OCTEON_SOC

					 !MACH_LOONGSON64 && !MACH_LOONGSON32 && \

					 !MIPS_MALTA && !CAVIUM_OCTEON_SOC

	default MIPS_CMDLINE_FROM_BOOTLOADER



	config MIPS_CMDLINE_FROM_DTB

arch/mips/include/asm/cpu-type.h

+1 −2
Original line number Diff line number Diff line
@@ -24,8 +24,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) 
	case CPU_LOONGSON64:

#endif



#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \

    defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)

#ifdef CONFIG_SYS_HAS_CPU_LOONGSON32

	case CPU_LOONGSON32:

#endif

arch/mips/include/asm/mach-loongson32/irq.h

deleted100644 → 0
+0 −107
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * IRQ mappings for Loongson 1

 */



#ifndef __ASM_MACH_LOONGSON32_IRQ_H

#define __ASM_MACH_LOONGSON32_IRQ_H



/*

 * CPU core Interrupt Numbers

 */

#define MIPS_CPU_IRQ_BASE		0

#define MIPS_CPU_IRQ(x)			(MIPS_CPU_IRQ_BASE + (x))



#define SOFTINT0_IRQ			MIPS_CPU_IRQ(0)

#define SOFTINT1_IRQ			MIPS_CPU_IRQ(1)

#define INT0_IRQ			MIPS_CPU_IRQ(2)

#define INT1_IRQ			MIPS_CPU_IRQ(3)

#define INT2_IRQ			MIPS_CPU_IRQ(4)

#define INT3_IRQ			MIPS_CPU_IRQ(5)

#define INT4_IRQ			MIPS_CPU_IRQ(6)

#define TIMER_IRQ			MIPS_CPU_IRQ(7)		/* cpu timer */



#define MIPS_CPU_IRQS		(MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)



/*

 * INT0~3 Interrupt Numbers

 */

#define LS1X_IRQ_BASE			MIPS_CPU_IRQS

#define LS1X_IRQ(n, x)			(LS1X_IRQ_BASE + (n << 5) + (x))



#define LS1X_UART0_IRQ			LS1X_IRQ(0, 2)

#if defined(CONFIG_LOONGSON1_LS1B)

#define LS1X_UART1_IRQ			LS1X_IRQ(0, 3)

#define LS1X_UART2_IRQ			LS1X_IRQ(0, 4)

#define LS1X_UART3_IRQ			LS1X_IRQ(0, 5)

#elif defined(CONFIG_LOONGSON1_LS1C)

#define LS1X_UART1_IRQ			LS1X_IRQ(0, 4)

#define LS1X_UART2_IRQ			LS1X_IRQ(0, 5)

#endif

#define LS1X_CAN0_IRQ			LS1X_IRQ(0, 6)

#define LS1X_CAN1_IRQ			LS1X_IRQ(0, 7)

#define LS1X_SPI0_IRQ			LS1X_IRQ(0, 8)

#define LS1X_SPI1_IRQ			LS1X_IRQ(0, 9)

#define LS1X_AC97_IRQ			LS1X_IRQ(0, 10)

#define LS1X_DMA0_IRQ			LS1X_IRQ(0, 13)

#define LS1X_DMA1_IRQ			LS1X_IRQ(0, 14)

#define LS1X_DMA2_IRQ			LS1X_IRQ(0, 15)

#if defined(CONFIG_LOONGSON1_LS1C)

#define LS1X_NAND_IRQ			LS1X_IRQ(0, 16)

#endif

#define LS1X_PWM0_IRQ			LS1X_IRQ(0, 17)

#define LS1X_PWM1_IRQ			LS1X_IRQ(0, 18)

#define LS1X_PWM2_IRQ			LS1X_IRQ(0, 19)

#define LS1X_PWM3_IRQ			LS1X_IRQ(0, 20)

#define LS1X_RTC_INT0_IRQ		LS1X_IRQ(0, 21)

#define LS1X_RTC_INT1_IRQ		LS1X_IRQ(0, 22)

#define LS1X_RTC_INT2_IRQ		LS1X_IRQ(0, 23)

#if defined(CONFIG_LOONGSON1_LS1B)

#define LS1X_TOY_INT0_IRQ		LS1X_IRQ(0, 24)

#define LS1X_TOY_INT1_IRQ		LS1X_IRQ(0, 25)

#define LS1X_TOY_INT2_IRQ		LS1X_IRQ(0, 26)

#define LS1X_RTC_TICK_IRQ		LS1X_IRQ(0, 27)

#define LS1X_TOY_TICK_IRQ		LS1X_IRQ(0, 28)

#define LS1X_UART4_IRQ			LS1X_IRQ(0, 29)

#define LS1X_UART5_IRQ			LS1X_IRQ(0, 30)

#elif defined(CONFIG_LOONGSON1_LS1C)

#define LS1X_UART3_IRQ			LS1X_IRQ(0, 29)

#define LS1X_ADC_IRQ			LS1X_IRQ(0, 30)

#define LS1X_SDIO_IRQ			LS1X_IRQ(0, 31)

#endif



#define LS1X_EHCI_IRQ			LS1X_IRQ(1, 0)

#define LS1X_OHCI_IRQ			LS1X_IRQ(1, 1)

#if defined(CONFIG_LOONGSON1_LS1B)

#define LS1X_GMAC0_IRQ			LS1X_IRQ(1, 2)

#define LS1X_GMAC1_IRQ			LS1X_IRQ(1, 3)

#elif defined(CONFIG_LOONGSON1_LS1C)

#define LS1X_OTG_IRQ			LS1X_IRQ(1, 2)

#define LS1X_GMAC0_IRQ			LS1X_IRQ(1, 3)

#define LS1X_CAM_IRQ			LS1X_IRQ(1, 4)

#define LS1X_UART4_IRQ			LS1X_IRQ(1, 5)

#define LS1X_UART5_IRQ			LS1X_IRQ(1, 6)

#define LS1X_UART6_IRQ			LS1X_IRQ(1, 7)

#define LS1X_UART7_IRQ			LS1X_IRQ(1, 8)

#define LS1X_UART8_IRQ			LS1X_IRQ(1, 9)

#define LS1X_UART9_IRQ			LS1X_IRQ(1, 13)

#define LS1X_UART10_IRQ			LS1X_IRQ(1, 14)

#define LS1X_UART11_IRQ			LS1X_IRQ(1, 15)

#define LS1X_I2C0_IRQ			LS1X_IRQ(1, 17)

#define LS1X_I2C1_IRQ			LS1X_IRQ(1, 18)

#define LS1X_I2C2_IRQ			LS1X_IRQ(1, 19)

#endif



#if defined(CONFIG_LOONGSON1_LS1B)

#define INTN	4

#elif defined(CONFIG_LOONGSON1_LS1C)

#define INTN	5

#endif



#define LS1X_IRQS		(LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)



#define NR_IRQS			(MIPS_CPU_IRQS + LS1X_IRQS)



#endif /* __ASM_MACH_LOONGSON32_IRQ_H */

arch/mips/include/asm/mach-loongson32/loongson1.h

deleted100644 → 0
+0 −50
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * Register mappings for Loongson 1

 */



#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H

#define __ASM_MACH_LOONGSON32_LOONGSON1_H



#if defined(CONFIG_LOONGSON1_LS1B)

#define DEFAULT_MEMSIZE			64	/* If no memsize provided */

#elif defined(CONFIG_LOONGSON1_LS1C)

#define DEFAULT_MEMSIZE			32

#endif



/* Loongson 1 Register Bases */

#define LS1X_MUX_BASE			0x1fd00420

#define LS1X_INTC_BASE			0x1fd01040

#define LS1X_GPIO0_BASE			0x1fd010c0

#define LS1X_GPIO1_BASE			0x1fd010c4

#define LS1X_DMAC_BASE			0x1fd01160

#define LS1X_CBUS_BASE			0x1fd011c0

#define LS1X_EHCI_BASE			0x1fe00000

#define LS1X_OHCI_BASE			0x1fe08000

#define LS1X_GMAC0_BASE			0x1fe10000

#define LS1X_GMAC1_BASE			0x1fe20000



#define LS1X_UART0_BASE			0x1fe40000

#define LS1X_UART1_BASE			0x1fe44000

#define LS1X_UART2_BASE			0x1fe48000

#define LS1X_UART3_BASE			0x1fe4c000

#define LS1X_CAN0_BASE			0x1fe50000

#define LS1X_CAN1_BASE			0x1fe54000

#define LS1X_I2C0_BASE			0x1fe58000

#define LS1X_I2C1_BASE			0x1fe68000

#define LS1X_I2C2_BASE			0x1fe70000

#define LS1X_PWM0_BASE			0x1fe5c000

#define LS1X_PWM1_BASE			0x1fe5c010

#define LS1X_PWM2_BASE			0x1fe5c020

#define LS1X_PWM3_BASE			0x1fe5c030

#define LS1X_WDT_BASE			0x1fe5c060

#define LS1X_RTC_BASE			0x1fe64000

#define LS1X_AC97_BASE			0x1fe74000

#define LS1X_NAND_BASE			0x1fe78000

#define LS1X_CLK_BASE			0x1fe78030



#include <regs-mux.h>



#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */