Commit 85ffc6e4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'v6.12-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 

Pull crypto update from Herbert Xu"
 "API:
   - Make self-test asynchronous

  Algorithms:
   - Remove MPI functions added for SM3
   - Add allocation error checks to remaining MPI functions (introduced
     for SM3)
   - Set default Jitter RNG OSR to 3

  Drivers:
   - Add hwrng driver for Rockchip RK3568 SoC
   - Allow disabling SR-IOV VFs through sysfs in qat
   - Fix device reset bugs in hisilicon
   - Fix authenc key parsing by using generic helper in octeontx*

  Others:
   - Fix xor benchmarking on parisc"

* tag 'v6.12-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (96 commits)
  crypto: n2 - Set err to EINVAL if snprintf fails for hmac
  crypto: camm/qi - Use ERR_CAST() to return error-valued pointer
  crypto: mips/crc32 - Clean up useless assignment operations
  crypto: qcom-rng - rename *_of_data to *_match_data
  crypto: qcom-rng - fix support for ACPI-based systems
  dt-bindings: crypto: qcom,prng: document support for SA8255p
  crypto: aegis128 - Fix indentation issue in crypto_aegis128_process_crypt()
  crypto: octeontx* - Select CRYPTO_AUTHENC
  crypto: testmgr - Hide ENOENT errors
  crypto: qat - Remove trailing space after \n newline
  crypto: hisilicon/sec - Remove trailing space after \n newline
  crypto: algboss - Pass instance creation error up
  crypto: api - Fix generic algorithm self-test races
  crypto: hisilicon/qm - inject error before stopping queue
  crypto: hisilicon/hpre - mask cluster timeout error
  crypto: hisilicon/qm - reset device before enabling it
  crypto: hisilicon/trng - modifying the order of header files
  crypto: hisilicon - add a lock for the qp send operation
  crypto: hisilicon - fix missed error branch
  crypto: ccp - do not request interrupt on cmd completion when irqs disabled
  ...
parents 94106455 ce212d2a

Documentation/devicetree/bindings/crypto/fsl,sec-v4.0.yaml

+4 −1
Original line number Diff line number Diff line
@@ -137,7 +137,10 @@ patternProperties: 
          - const: fsl,sec-v4.0-rtic



      reg:

        maxItems: 1

        items:

          - description: RTIC control and status register space.

          - description: RTIC recoverable error indication register space.

        minItems: 1



      ranges:

        maxItems: 1

Documentation/devicetree/bindings/crypto/qcom,prng.yaml

+1 −0
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@@ -17,6 +17,7 @@ properties: 
          - qcom,prng-ee  # 8996 and later using EE

      - items:

          - enum:

              - qcom,sa8255p-trng

              - qcom,sa8775p-trng

              - qcom,sc7280-trng

              - qcom,sm8450-trng

Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml

0 → 100644
+61 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/rng/rockchip,rk3568-rng.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3568 TRNG



description: True Random Number Generator on Rockchip RK3568 SoC



maintainers:

  - Aurelien Jarno <aurelien@aurel32.net>

  - Daniel Golle <daniel@makrotopia.org>



properties:

  compatible:

    enum:

      - rockchip,rk3568-rng



  reg:

    maxItems: 1



  clocks:

    items:

      - description: TRNG clock

      - description: TRNG AHB clock



  clock-names:

    items:

      - const: core

      - const: ahb



  resets:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/rk3568-cru.h>

    bus {

      #address-cells = <2>;

      #size-cells = <2>;



      rng@fe388000 {

        compatible = "rockchip,rk3568-rng";

        reg = <0x0 0xfe388000 0x0 0x4000>;

        clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;

        clock-names = "core", "ahb";

        resets = <&cru SRST_TRNG_NS>;

      };

    };



...

MAINTAINERS

+7 −0
Original line number Diff line number Diff line
@@ -19807,6 +19807,13 @@ F: Documentation/userspace-api/media/v4l/metafmt-rkisp1.rst 
F:	drivers/media/platform/rockchip/rkisp1

F:	include/uapi/linux/rkisp1-config.h









ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT









M:	Daniel Golle <daniel@makrotopia.org>









M:	Aurelien Jarno <aurelien@aurel32.net>









S:	Maintained









F:	Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml









F:	drivers/char/hw_random/rockchip-rng.c

















ROCKCHIP RASTER 2D GRAPHIC ACCELERATION UNIT DRIVER









M:	Jacob Chen <jacob-chen@iotwrt.com>









M:	Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

























arch/arm/crypto/Kconfig



+10
−4






























Original line number
Diff line number
Diff line







@@ -166,10 +166,9 @@ config CRYPTO_AES_ARM







config CRYPTO_AES_ARM_BS









	tristate "Ciphers: AES, modes: ECB/CBC/CTR/XTS (bit-sliced NEON)"









	depends on KERNEL_MODE_NEON









	select CRYPTO_AES_ARM









	select CRYPTO_SKCIPHER









	select CRYPTO_LIB_AES









	select CRYPTO_AES









	select CRYPTO_CBC









	select CRYPTO_SIMD









	help









	  Length-preserving ciphers: AES cipher algorithms (FIPS-197)








@@ -183,8 +182,15 @@ config CRYPTO_AES_ARM_BS







	  Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode









	  and for XTS mode encryption, CBC and XTS mode decryption speedup is









	  around 25%. (CBC encryption speed is not affected by this driver.)









	  This implementation does not rely on any lookup tables so it is









	  believed to be invulnerable to cache timing attacks.



















	  The bit sliced AES code does not use lookup tables, so it is believed









	  to be invulnerable to cache timing attacks. However, since the bit









	  sliced AES code cannot process single blocks efficiently, in certain









	  cases table-based code with some countermeasures against cache timing









	  attacks will still be used as a fallback method; specifically CBC









	  encryption (not CBC decryption), the encryption of XTS tweaks, XTS









	  ciphertext stealing when the message isn't a multiple of 16 bytes, and









	  CTR when invoked in a context in which NEON instructions are unusable.



















config CRYPTO_AES_ARM_CE









	tristate "Ciphers: AES, modes: ECB/CBC/CTS/CTR/XTS (ARMv8 Crypto Extensions)"