Commit 86637727 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a78000: Fix SCIF brg_int clocks 



According to the documentation, the internal clock input for the BRG is
SGASYNCD4_PERW_BUSφ.

Fixes: c13a643e2c491f5b ("arm64: dts: renesas: Add R8A78000 SoC support")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/459d360a8332f92b3766b30814e7e1c76169aaf7.1767719254.git.geert+renesas@glider.be
parent 254f4963

arch/arm64/boot/dts/renesas/r8a78000.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -699,7 +699,7 @@ scif0: serial@c0700000 { 
				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0700000 0 0x40>;

			interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";

		};
@@ -709,7 +709,7 @@ scif1: serial@c0704000 { 
				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0704000 0 0x40>;

			interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";

		};
@@ -719,7 +719,7 @@ scif3: serial@c0708000 { 
				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc0708000 0 0x40>;

			interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";

		};
@@ -729,7 +729,7 @@ scif4: serial@c070c000 { 
				     "renesas,rcar-gen5-scif", "renesas,scif";

			reg = <0 0xc070c000 0 0x40>;

			interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;

			clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			status = "disabled";

		};