Commit 8690bbcf authored by Mathieu Desnoyers's avatar Mathieu Desnoyers Committed by Andrew Morton
Browse files

Introduce cpu_dcache_is_aliasing() across all architectures 

Introduce a generic way to query whether the data cache is virtually
aliased on all architectures. Its purpose is to ensure that subsystems
which are incompatible with virtually aliased data caches (e.g. FS_DAX)
can reliably query this.

For data cache aliasing, there are three scenarios dependending on the
architecture. Here is a breakdown based on my understanding:

A) The data cache is always aliasing:

* arc
* csky
* m68k (note: shared memory mappings are incoherent ? SHMLBA is missing there.)
* sh
* parisc

B) The data cache aliasing is statically known or depends on querying CPU
   state at runtime:

* arm (cache_is_vivt() || cache_is_vipt_aliasing())
* mips (cpu_has_dc_aliases)
* nios2 (NIOS2_DCACHE_SIZE > PAGE_SIZE)
* sparc32 (vac_cache_size > PAGE_SIZE)
* sparc64 (L1DCACHE_SIZE > PAGE_SIZE)
* xtensa (DCACHE_WAY_SIZE > PAGE_SIZE)

C) The data cache is never aliasing:

* alpha
* arm64 (aarch64)
* hexagon
* loongarch (but with incoherent write buffers, which are disabled since
             commit d23b7795 ("LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE"))
* microblaze
* openrisc
* powerpc
* riscv
* s390
* um
* x86

Require architectures in A) and B) to select ARCH_HAS_CPU_CACHE_ALIASING and
implement "cpu_dcache_is_aliasing()".

Architectures in C) don't select ARCH_HAS_CPU_CACHE_ALIASING, and thus
cpu_dcache_is_aliasing() simply evaluates to "false".

Note that this leaves "cpu_icache_is_aliasing()" to be implemented as future
work. This would be useful to gate features like XIP on architectures
which have aliasing CPU dcache-icache but not CPU dcache-dcache.

Use "cpu_dcache" and "cpu_cache" rather than just "dcache" and "cache"
to clarify that we really mean "CPU data cache" and "CPU cache" to
eliminate any possible confusion with VFS "dentry cache" and "page
cache".

Link: https://lore.kernel.org/lkml/20030910210416.GA24258@mail.jlokier.co.uk/
Link: https://lkml.kernel.org/r/20240215144633.96437-9-mathieu.desnoyers@efficios.com


Fixes: d92576f1 ("dax: does not work correctly with virtual aliasing caches")
Signed-off-by: default avatarMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Alasdair Kergon <agk@redhat.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Dave Chinner <david@fromorbit.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: kernel test robot <lkp@intel.com>
Cc: Michael Sclafani <dm-devel@lists.linux.dev>
Cc: Mike Snitzer <snitzer@kernel.org>
Cc: Mikulas Patocka <mpatocka@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent 1df4ca01

arch/arc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
config ARC

	def_bool y

	select ARC_TIMERS

	select ARCH_HAS_CPU_CACHE_ALIASING

	select ARCH_HAS_CACHE_LINE_SIZE

	select ARCH_HAS_DEBUG_VM_PGTABLE

	select ARCH_HAS_DMA_PREP_COHERENT

arch/arc/include/asm/cachetype.h

0 → 100644
+9 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef __ASM_ARC_CACHETYPE_H

#define __ASM_ARC_CACHETYPE_H



#include <linux/types.h>



#define cpu_dcache_is_aliasing()	true



#endif

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ config ARM 
	select ARCH_32BIT_OFF_T

	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND

	select ARCH_HAS_BINFMT_FLAT

	select ARCH_HAS_CPU_CACHE_ALIASING

	select ARCH_HAS_CPU_FINALIZE_INIT if MMU

	select ARCH_HAS_CURRENT_STACK_POINTER

	select ARCH_HAS_DEBUG_VIRTUAL if MMU

arch/arm/include/asm/cachetype.h

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ extern unsigned int cacheid; 
#define icache_is_vipt_aliasing()	cacheid_is(CACHEID_VIPT_I_ALIASING)

#define icache_is_pipt()		cacheid_is(CACHEID_PIPT)



#define cpu_dcache_is_aliasing()	(cache_is_vivt() || cache_is_vipt_aliasing())



/*

 * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture

 * Mask out support which will never be present on newer CPUs.

arch/csky/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
config CSKY

	def_bool y

	select ARCH_32BIT_OFF_T

	select ARCH_HAS_CPU_CACHE_ALIASING

	select ARCH_HAS_DMA_PREP_COHERENT

	select ARCH_HAS_GCOV_PROFILE_ALL

	select ARCH_HAS_SYNC_DMA_FOR_CPU