Commit 86b1ec23 authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Stephen Boyd
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dt-bindings: clock: xilinx: add versal compatible

parent b85ea95d
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+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ properties:
      - xlnx,clocking-wizard
      - xlnx,clocking-wizard-v5.2
      - xlnx,clocking-wizard-v6.0
      - xlnx,versal-clk-wizard


  reg: