Commit 86c54c84 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v6.9-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull clocksource/event driver updates from Daniel Lezcano:

  - Fix -Wunused-but-set-variable warning for the iMX GPT timer (Daniel
    Lezcano)

  - Add Pixel6 compatible string for Exynos 4210 MCT timer (Peter Griffin)

  - Fix all kernel-doc warnings and misuse of comment format (Randy
    Dunlap)

  - Document in the DT bindings the interrupt used for input capture
    interrupt and udpate the example to match the reality (Geert
    Uytterhoeven)

  - Document RZ/Five SoC DT bindings (Lad Prabhakar)

  - Add DT bindings support for the i.MX95, reorganize the driver to
    move globale variables to a timer private structure and introduce
    the i.MX95 timer support (Peng Fan)

  - Fix prescalar value to conform to the ARM global timer
    documentation. Fix data types and comparison, guard the divide by
    zero code section and use the available macros for bit manipulation
    (Martin Blumenstingl)

  - Add Ralink SoCs system tick counter (Sergio Paracuellos)

  - Add support for cadence TTC PWM (Mubin Sayyed)

  - Clear timer interrupt on timer initialization to prevent the
    interrupt to fire during setup (Ley Foon Tan)

Link: https://lore.kernel.org/r/5552010a-1ce2-46a1-a740-a69f2e9a2cf2@linaro.org
parents 8ca18367 8248ca30

Documentation/devicetree/bindings/timer/cdns,ttc.yaml

+21 −1
Original line number Diff line number Diff line
@@ -32,12 +32,23 @@ properties: 
    description: |

      Bit width of the timer, necessary if not 16.



  "#pwm-cells":

    const: 3



required:

  - compatible

  - reg

  - interrupts

  - clocks



allOf:

  - if:

      not:

        required:

          - "#pwm-cells"

    then:

      required:

        - interrupts



additionalProperties: false



examples:
@@ -50,3 +61,12 @@ examples: 
        clocks = <&cpu_clk 3>;

        timer-width = <32>;

    };



  - |

    pwm: pwm@f8002000 {

        compatible = "cdns,ttc";

        reg = <0xf8002000 0x1000>;

        clocks = <&cpu_clk 3>;

        timer-width = <32>;

        #pwm-cells = <3>;

    };

Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml

+3 −1
Original line number Diff line number Diff line
@@ -18,7 +18,9 @@ description: | 


properties:

  compatible:

    const: nxp,sysctr-timer

    enum:

      - nxp,imx95-sysctr-timer

      - nxp,sysctr-timer



  reg:

    maxItems: 1

Documentation/devicetree/bindings/timer/ralink,cevt-systick.yaml

0 → 100644
+38 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/timer/ralink,cevt-systick.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: System tick counter present in Ralink family SoCs



maintainers:

  - Sergio Paracuellos <sergio.paracuellos@gmail.com>



properties:

  compatible:

    const: ralink,cevt-systick



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts



additionalProperties: false



examples:

  - |

    systick@d00 {

        compatible = "ralink,cevt-systick";

        reg = <0xd00 0x10>;



        interrupt-parent = <&cpuintc>;

        interrupts = <7>;

    };

...

Documentation/devicetree/bindings/timer/renesas,ostm.yaml

+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ properties: 
      - enum:

          - renesas,r7s72100-ostm  # RZ/A1H

          - renesas,r7s9210-ostm   # RZ/A2M

          - renesas,r9a07g043-ostm # RZ/G2UL

          - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five

          - renesas,r9a07g044-ostm # RZ/G2{L,LC}

          - renesas,r9a07g054-ostm # RZ/V2L

      - const: renesas,ostm        # Generic

Documentation/devicetree/bindings/timer/renesas,tmu.yaml

+16 −2
Original line number Diff line number Diff line
@@ -46,7 +46,19 @@ properties: 


  interrupts:

    minItems: 2

    maxItems: 3

    items:

      - description: Underflow interrupt, channel 0

      - description: Underflow interrupt, channel 1

      - description: Underflow interrupt, channel 2

      - description: Input capture interrupt, channel 2



  interrupt-names:

    minItems: 2

    items:

      - const: tuni0

      - const: tuni1

      - const: tuni2

      - const: ticpi2



  clocks:

    maxItems: 1
@@ -100,7 +112,9 @@ examples: 
            reg = <0xffd80000 0x30>;

            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

                         <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";

            clocks = <&mstp0_clks R8A7779_CLK_TMU0>;

            clock-names = "fck";

            power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;