Commit 86e122c0 authored Nov 12, 2021 by Biju Das Committed by Geert Uytterhoeven Nov 19, 2021

clk: renesas: rzg2l: Add CPG_PL1_DDIV macro



Core clock "I" is sourced from  CPG_PL1_DDIV which controls CPU
frequency. Define CPG_PL1_DDIV, so that we can register it as a
clock divider in later patch.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211112081003.15453-2-biju.das.jz@bp.renesas.com


Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

parent e5f7e81e

drivers/clk/renesas/rzg2l-cpg.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -9,6 +9,7 @@
		#ifndef __RENESAS_RZG2L_CPG_H__
		#define __RENESAS_RZG2L_CPG_H__

		#define CPG_PL1_DDIV (0x200)
		#define CPG_PL2_DDIV (0x204)
		#define CPG_PL3A_DDIV (0x208)
		#define CPG_PL2SDHI_DSEL (0x218)
		@@ -29,6 +30,7 @@

		#define DDIV_PACK(offset, bitpos, size) \
		(((offset) << 20) \| ((bitpos) << 12) \| ((size) << 8))
		#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)
		#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
		#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
		#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)