Commit 86e70849 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Vinod Koul
Browse files

phy: renesas: rcar-gen3-usb2: Set timing registers only once 



phy-rcar-gen3-usb2 driver exports 4 PHYs. The timing registers are common
to all PHYs. There is no need to set them every time a PHY is initialized.
Set timing register only when the 1st PHY is initialized.

Fixes: f3b5a8d9 ("phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver")
Cc: stable@vger.kernel.org
Reviewed-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20250507125032.565017-6-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9ce71e85

drivers/phy/renesas/phy-rcar-gen3-usb2.c

+5 −2
Original line number Diff line number Diff line
@@ -467,8 +467,11 @@ static int rcar_gen3_phy_usb2_init(struct phy *p) 
	val = readl(usb2_base + USB2_INT_ENABLE);

	val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits;

	writel(val, usb2_base + USB2_INT_ENABLE);



	if (!rcar_gen3_is_any_rphy_initialized(channel)) {

		writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);

		writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);

	}



	/* Initialize otg part (only if we initialize a PHY with IRQs). */

	if (rphy->int_enable_bits)