Unverified Commit 86f9823d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'tegra-for-7.1-soc' of... 

Merge tag 'tegra-for-7.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

soc/tegra: Changes for v7.1-rc1

A number of fixes went into this for the PMC and CBB drivers. The PMC
driver also gains support for Tegra264 and a Kconfig symbol for the
upcoming Tegra238 is added. The various per-generation Kconfig symbols
are now also enabled by default for ARCH_TEGRA in order to reduce the
number of configuration options that need to be explicitly enabled.

* tag 'tegra-for-7.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  MAINTAINERS: Change email address for Thierry Reding
  soc/tegra: pmc: Add IO pads for Tegra264
  soc/tegra: pmc: Rename has_impl_33v_pwr flag
  soc/tegra: pmc: Refactor IO pad voltage control
  soc/tegra: pmc: Add Tegra264 wake events
  soc/tegra: pmc: Add AOWAKE regs for Tegra264
  soc/tegra: pmc: Add support for SoC specific AOWAKE offsets
  soc/tegra: pmc: Remove unused AOWAKE definitions
  soc/tegra: pmc: Add kerneldoc for wake-up variables
  soc/tegra: pmc: Correct function names in kerneldoc
  soc/tegra: pmc: Add kerneldoc for reboot notifier
  soc/tegra: common: Add Tegra114 support to devm_tegra_core_dev_init_opp_table
  soc/tegra: pmc: Enable core domain support for Tegra114
  soc/tegra: cbb: Fix cross-fabric target timeout lookup
  soc/tegra: cbb: Fix incorrect ARRAY_SIZE in fabric lookup tables
  soc/tegra: cbb: Set ERD on resume for err interrupt
  soc/tegra: cbb: Add support for CBB fabrics in Tegra238
  soc/tegra: Add Tegra238 Kconfig symbol
  soc/tegra: Make ARCH_TEGRA_SOC_FOO defaults for NVIDIA Tegra

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 84a5fe2e 4b23febb

MAINTAINERS

+7 −7
Original line number Diff line number Diff line
@@ -8649,7 +8649,7 @@ F: drivers/phy/mediatek/phy-mtk-hdmi* 
F:	drivers/phy/mediatek/phy-mtk-mipi*









DRM DRIVERS FOR NVIDIA TEGRA









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Thierry Reding <thierry.reding@kernel.org>









M:	Mikko Perttunen <mperttunen@nvidia.com>









L:	dri-devel@lists.freedesktop.org









L:	linux-tegra@vger.kernel.org








@@ -20247,7 +20247,7 @@ S:	Maintained







F:	drivers/pci/controller/*mvebu*

















PCI DRIVER FOR NVIDIA TEGRA









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Thierry Reding <thierry.reding@kernel.org>









L:	linux-tegra@vger.kernel.org









L:	linux-pci@vger.kernel.org









S:	Supported








@@ -25951,7 +25951,7 @@ F:	include/linux/tee_drv.h







F:	include/uapi/linux/tee.h

















TEGRA ARCHITECTURE SUPPORT









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Thierry Reding <thierry.reding@kernel.org>









M:	Jonathan Hunter <jonathanh@nvidia.com>









L:	linux-tegra@vger.kernel.org









S:	Supported








@@ -25983,7 +25983,7 @@ S:	Supported







F:	drivers/i2c/busses/i2c-tegra.c

















TEGRA IOMMU DRIVERS









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Thierry Reding <thierry.reding@kernel.org>









R:	Krishna Reddy <vdumpa@nvidia.com>









L:	linux-tegra@vger.kernel.org









S:	Supported








@@ -26004,12 +26004,12 @@ F:	Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml







F:	drivers/mtd/nand/raw/tegra_nand.c

















TEGRA PWM DRIVER









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Thierry Reding <thierry.reding@kernel.org>









S:	Supported









F:	drivers/pwm/pwm-tegra.c

















TEGRA QUAD SPI DRIVER









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Thierry Reding <thierry.reding@kernel.org>









M:	Jonathan Hunter <jonathanh@nvidia.com>









M:	Sowjanya Komatineni <skomatineni@nvidia.com>









L:	linux-tegra@vger.kernel.org








@@ -26027,7 +26027,7 @@ S:	Supported







F:	drivers/spi/spi-tegra*

















TEGRA VIDEO DRIVER









M:	Thierry Reding <thierry.reding@gmail.com>









M:	Thierry Reding <thierry.reding@kernel.org>









M:	Jonathan Hunter <jonathanh@nvidia.com>









M:	Sowjanya Komatineni <skomatineni@nvidia.com>









M:	Luca Ceresoli <luca.ceresoli@bootlin.com>

























drivers/soc/tegra/Kconfig



+20
−0






























Original line number
Diff line number
Diff line







@@ -6,6 +6,7 @@ if ARM

















config ARCH_TEGRA_2x_SOC









	bool "Enable support for Tegra20 family"









	default ARCH_TEGRA









	select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP









	select ARM_ERRATA_720789









	select ARM_ERRATA_754327 if SMP








@@ -23,6 +24,7 @@ config ARCH_TEGRA_2x_SOC

















config ARCH_TEGRA_3x_SOC









	bool "Enable support for Tegra30 family"









	default ARCH_TEGRA









	select ARM_ERRATA_754322









	select ARM_ERRATA_764369 if SMP









	select PINCTRL_TEGRA30








@@ -37,6 +39,7 @@ config ARCH_TEGRA_3x_SOC

















config ARCH_TEGRA_114_SOC









	bool "Enable support for Tegra114 family"









	default ARCH_TEGRA









	select ARM_ERRATA_798181 if SMP









	select HAVE_ARM_ARCH_TIMER









	select PINCTRL_TEGRA114








@@ -49,6 +52,7 @@ config ARCH_TEGRA_114_SOC

















config ARCH_TEGRA_124_SOC









	bool "Enable support for Tegra124 family"









	default ARCH_TEGRA









	select HAVE_ARM_ARCH_TIMER









	select PINCTRL_TEGRA124









	select SOC_TEGRA_FLOWCTRL








@@ -65,6 +69,7 @@ if ARM64

















config ARCH_TEGRA_132_SOC









	bool "NVIDIA Tegra132 SoC"









	default ARCH_TEGRA









	select PINCTRL_TEGRA124









	select SOC_TEGRA_FLOWCTRL









	select SOC_TEGRA_PMC








@@ -76,6 +81,7 @@ config ARCH_TEGRA_132_SOC

















config ARCH_TEGRA_210_SOC









	bool "NVIDIA Tegra210 SoC"









	default ARCH_TEGRA









	select PINCTRL_TEGRA210









	select SOC_TEGRA_FLOWCTRL









	select SOC_TEGRA_PMC








@@ -95,6 +101,7 @@ config ARCH_TEGRA_210_SOC

















config ARCH_TEGRA_186_SOC









	bool "NVIDIA Tegra186 SoC"









	default ARCH_TEGRA









	depends on !CPU_BIG_ENDIAN









	select PINCTRL_TEGRA186









	select MAILBOX








@@ -109,6 +116,7 @@ config ARCH_TEGRA_186_SOC

















config ARCH_TEGRA_194_SOC









	bool "NVIDIA Tegra194 SoC"









	default ARCH_TEGRA









	depends on !CPU_BIG_ENDIAN









	select MAILBOX









	select PINCTRL_TEGRA194








@@ -118,6 +126,7 @@ config ARCH_TEGRA_194_SOC

















config ARCH_TEGRA_234_SOC









	bool "NVIDIA Tegra234 SoC"









	default ARCH_TEGRA









	depends on !CPU_BIG_ENDIAN









	select MAILBOX









	select PINCTRL_TEGRA234








@@ -125,13 +134,24 @@ config ARCH_TEGRA_234_SOC







	help









	  Enable support for the NVIDIA Tegra234 SoC.



















config ARCH_TEGRA_238_SOC









	bool "NVIDIA Tegra238 SoC"









	default ARCH_TEGRA









	depends on !CPU_BIG_ENDIAN









	select MAILBOX









	select SOC_TEGRA_PMC









	help









	  Enable support for the NVIDIA Tegra238 SoC.



















config ARCH_TEGRA_241_SOC









	bool "NVIDIA Tegra241 SoC"









	default ARCH_TEGRA









	help









	  Enable support for the NVIDIA Tegra241 SoC.



















config ARCH_TEGRA_264_SOC









	bool "NVIDIA Tegra264 SoC"









	default ARCH_TEGRA









	depends on !CPU_BIG_ENDIAN









	select MAILBOX









	select SOC_TEGRA_PMC
































drivers/soc/tegra/cbb/tegra234-cbb.c



+166
−3






























Original line number
Diff line number
Diff line







@@ -89,6 +89,15 @@ enum tegra234_cbb_fabric_ids {







	T234_MAX_FABRIC_ID,









};



















enum tegra238_cbb_fabric_ids {









	T238_CBB_FABRIC_ID  = 0,









	T238_AON_FABRIC_ID  = 4,









	T238_PSC_FABRIC_ID  = 5,









	T238_BPMP_FABRIC_ID = 6,









	T238_APE_FABRIC_ID  = 7,









	T238_MAX_FABRIC_ID,









};



















enum tegra264_cbb_fabric_ids {









	T264_SYSTEM_CBB_FABRIC_ID,









	T264_TOP_0_CBB_FABRIC_ID,








@@ -313,12 +322,37 @@ static void tegra234_cbb_lookup_apbslv(struct seq_file *file, const char *target







	}









}



















static struct tegra234_cbb *tegra234_cbb_get_fabric(u8 fab_id)









{









	struct tegra_cbb *entry;



















	list_for_each_entry(entry, &cbb_list, node) {









		struct tegra234_cbb *priv = to_tegra234_cbb(entry);



















		if (priv->fabric->fab_id == fab_id)









			return priv;









	}



















	return NULL;









}



















static void tegra234_sw_lookup_target_timeout(struct seq_file *file, struct tegra234_cbb *cbb,









					      u8 target_id, u8 fab_id)









{









	const struct tegra234_target_lookup *map = cbb->fabric->fab_list[fab_id].target_map;









	struct tegra234_cbb *target_cbb = NULL;









	void __iomem *addr;



















	if (fab_id == cbb->fabric->fab_id)









		target_cbb = cbb;









	else









		target_cbb = tegra234_cbb_get_fabric(fab_id);



















	if (!target_cbb) {









		dev_err(cbb->base.dev, "could not find fabric for fab_id:%d\n", fab_id);









		return;









	}



















	if (target_id >= cbb->fabric->fab_list[fab_id].max_targets) {









		tegra_cbb_print_err(file, "\t  Invalid target_id:%d\n", target_id);









		return;








@@ -341,7 +375,7 @@ static void tegra234_sw_lookup_target_timeout(struct seq_file *file, struct tegr







	 *	e) Goto step-a till all bits are set.









	 */



















	addr = cbb->regs + map[target_id].offset;









	addr = target_cbb->regs + map[target_id].offset;



















	if (strstr(map[target_id].name, "AXI2APB")) {









		addr += APB_BLOCK_TMO_STATUS_0;








@@ -881,7 +915,7 @@ static const struct tegra234_fabric_lookup tegra234_cbb_fab_list[] = {







				 ARRAY_SIZE(tegra234_common_target_map) },









	[T234_AON_FABRIC_ID] = { "aon-fabric", true,









				 tegra234_aon_target_map,









				 ARRAY_SIZE(tegra234_bpmp_target_map) },









				 ARRAY_SIZE(tegra234_aon_target_map) },









	[T234_PSC_FABRIC_ID] = { "psc-fabric" },









	[T234_BPMP_FABRIC_ID] = { "bpmp-fabric", true,









				 tegra234_bpmp_target_map,








@@ -974,6 +1008,127 @@ static const struct tegra234_cbb_fabric tegra234_sce_fabric = {







	.firewall_wr_ctl = 0x288,









};



















static const struct tegra234_target_lookup tegra238_ape_target_map[] = {









	{ "AXI2APB", 0x00000 },









	{ "AGIC",    0x15000 },









	{ "AMC",     0x16000 },









	{ "AST0",    0x17000 },









	{ "AST1",    0x18000 },









	{ "AST2",    0x19000 },









	{ "CBB",     0x1A000 },









};



















static const struct tegra234_target_lookup tegra238_cbb_target_map[] = {









	{ "AON",         0x40000 },









	{ "APE",         0x50000 },









	{ "BPMP",        0x41000 },









	{ "HOST1X",      0x43000 },









	{ "STM",         0x44000 },









	{ "CBB_CENTRAL", 0x00000 },









	{ "PCIE_C0",     0x51000 },









	{ "PCIE_C1",     0x47000 },









	{ "PCIE_C2",     0x48000 },









	{ "PCIE_C3",     0x49000 },









	{ "GPU",         0x4C000 },









	{ "SMMU0",       0x4D000 },









	{ "SMMU1",       0x4E000 },









	{ "SMMU2",       0x4F000 },









	{ "PSC",         0x52000 },









	{ "AXI2APB_1",   0x70000 },









	{ "AXI2APB_12",  0x73000 },









	{ "AXI2APB_13",  0x74000 },









	{ "AXI2APB_15",  0x76000 },









	{ "AXI2APB_16",  0x77000 },









	{ "AXI2APB_18",  0x79000 },









	{ "AXI2APB_19",  0x7A000 },









	{ "AXI2APB_2",   0x7B000 },









	{ "AXI2APB_23",  0x7F000 },









	{ "AXI2APB_25",  0x80000 },









	{ "AXI2APB_26",  0x81000 },









	{ "AXI2APB_27",  0x82000 },









	{ "AXI2APB_28",  0x83000 },









	{ "AXI2APB_32",  0x87000 },









	{ "AXI2APB_33",  0x88000 },









	{ "AXI2APB_4",   0x8B000 },









	{ "AXI2APB_5",   0x8C000 },









	{ "AXI2APB_6",   0x93000 },









	{ "AXI2APB_9",   0x90000 },









	{ "AXI2APB_3",   0x91000 },









};



















static const struct tegra234_fabric_lookup tegra238_cbb_fab_list[] = {









	[T238_CBB_FABRIC_ID]  = { "cbb-fabric", true,









				  tegra238_cbb_target_map,









				  ARRAY_SIZE(tegra238_cbb_target_map) },









	[T238_AON_FABRIC_ID]  = { "aon-fabric", true,









				  tegra234_aon_target_map,









				  ARRAY_SIZE(tegra234_aon_target_map) },









	[T238_PSC_FABRIC_ID]  = { "psc-fabric" },









	[T238_BPMP_FABRIC_ID] = { "bpmp-fabric", true,









				  tegra234_bpmp_target_map,









				  ARRAY_SIZE(tegra234_bpmp_target_map) },









	[T238_APE_FABRIC_ID]  = { "ape-fabric", true,









				  tegra238_ape_target_map,









				  ARRAY_SIZE(tegra238_ape_target_map) },









};



















static const struct tegra234_cbb_fabric tegra238_aon_fabric = {









	.fab_id = T238_AON_FABRIC_ID,









	.fab_list = tegra238_cbb_fab_list,









	.initiator_id = tegra234_initiator_id,









	.errors = tegra234_cbb_errors,









	.max_errors = ARRAY_SIZE(tegra234_cbb_errors),









	.err_intr_enbl = 0x7,









	.err_status_clr = 0x3f,









	.notifier_offset = 0x17000,









	.firewall_base = 0x30000,









	.firewall_ctl = 0x8f0,









	.firewall_wr_ctl = 0x8e8,









};



















static const struct tegra234_cbb_fabric tegra238_ape_fabric = {









	.fab_id = T238_APE_FABRIC_ID,









	.fab_list = tegra238_cbb_fab_list,









	.initiator_id = tegra234_initiator_id,









	.errors = tegra234_cbb_errors,









	.max_errors = ARRAY_SIZE(tegra234_cbb_errors),









	.err_intr_enbl = 0xf,









	.err_status_clr = 0x3f,









	.notifier_offset = 0x1E000,









	.firewall_base = 0x30000,









	.firewall_ctl = 0xad0,









	.firewall_wr_ctl = 0xac8,









};



















static const struct tegra234_cbb_fabric tegra238_bpmp_fabric = {









	.fab_id = T238_BPMP_FABRIC_ID,









	.fab_list = tegra238_cbb_fab_list,









	.initiator_id = tegra234_initiator_id,









	.errors = tegra234_cbb_errors,









	.max_errors = ARRAY_SIZE(tegra234_cbb_errors),









	.err_intr_enbl = 0xf,









	.err_status_clr = 0x3f,









	.notifier_offset = 0x19000,









	.firewall_base = 0x30000,









	.firewall_ctl = 0x8f0,









	.firewall_wr_ctl = 0x8e8,









};



















static const struct tegra234_cbb_fabric tegra238_cbb_fabric = {









	.fab_id = T238_CBB_FABRIC_ID,









	.fab_list = tegra238_cbb_fab_list,









	.initiator_id = tegra234_initiator_id,









	.errors = tegra234_cbb_errors,









	.max_errors = ARRAY_SIZE(tegra234_cbb_errors),









	.err_intr_enbl = 0x3f,









	.err_status_clr = 0x3f,









	.notifier_offset = 0x60000,









	.off_mask_erd = 0x3d004,









	.firewall_base = 0x10000,









	.firewall_ctl = 0x2230,









	.firewall_wr_ctl = 0x2228,









};



















static const char * const tegra241_initiator_id[] = {









	[0x0] = "TZ",









	[0x1] = "CCPLEX",








@@ -1160,7 +1315,7 @@ static const struct tegra234_fabric_lookup tegra241_cbb_fab_list[] = {







	[T234_CBB_FABRIC_ID]  = { "cbb-fabric", true,









				  tegra241_cbb_target_map, ARRAY_SIZE(tegra241_cbb_target_map) },









	[T234_BPMP_FABRIC_ID] = { "bpmp-fabric", true,









				  tegra241_bpmp_target_map, ARRAY_SIZE(tegra241_cbb_target_map) },









				  tegra241_bpmp_target_map, ARRAY_SIZE(tegra241_bpmp_target_map) },









};









static const struct tegra234_cbb_fabric tegra241_cbb_fabric = {









	.fab_id = T234_CBB_FABRIC_ID,








@@ -1480,6 +1635,10 @@ static const struct of_device_id tegra234_cbb_dt_ids[] = {







	{ .compatible = "nvidia,tegra234-dce-fabric", .data = &tegra234_dce_fabric },









	{ .compatible = "nvidia,tegra234-rce-fabric", .data = &tegra234_rce_fabric },









	{ .compatible = "nvidia,tegra234-sce-fabric", .data = &tegra234_sce_fabric },









	{ .compatible = "nvidia,tegra238-aon-fabric", .data = &tegra238_aon_fabric },









	{ .compatible = "nvidia,tegra238-ape-fabric", .data = &tegra238_ape_fabric },









	{ .compatible = "nvidia,tegra238-bpmp-fabric", .data = &tegra238_bpmp_fabric },









	{ .compatible = "nvidia,tegra238-cbb-fabric", .data = &tegra238_cbb_fabric },









	{ .compatible = "nvidia,tegra264-sys-cbb-fabric", .data = &tegra264_sys_cbb_fabric },









	{ .compatible = "nvidia,tegra264-top0-cbb-fabric", .data = &tegra264_top0_cbb_fabric },









	{ .compatible = "nvidia,tegra264-uphy0-cbb-fabric", .data = &tegra264_uphy0_cbb_fabric },








@@ -1586,6 +1745,10 @@ static int __maybe_unused tegra234_cbb_resume_noirq(struct device *dev)







{









	struct tegra234_cbb *cbb = dev_get_drvdata(dev);



















	/* set ERD bit to mask SError and generate interrupt to report error */









	if (cbb->fabric->off_mask_erd)









		tegra234_cbb_mask_serror(cbb);



















	tegra234_cbb_error_enable(&cbb->base);



















	dev_dbg(dev, "%s resumed\n", cbb->fabric->fab_list[cbb->fabric->fab_id].name);
































drivers/soc/tegra/common.c



+3
−2






























Original line number
Diff line number
Diff line







@@ -118,7 +118,8 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,







		hw_version = BIT(tegra_sku_info.soc_process_id);









		config.supported_hw = &hw_version;









		config.supported_hw_count = 1;









	} else if (of_machine_is_compatible("nvidia,tegra30")) {









	} else if (of_machine_is_compatible("nvidia,tegra30") ||









		   of_machine_is_compatible("nvidia,tegra114")) {









		hw_version = BIT(tegra_sku_info.soc_speedo_id);









		config.supported_hw = &hw_version;









		config.supported_hw_count = 1;








@@ -131,7 +132,7 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,







	}



















	/*









	 * Tegra114+ doesn't support OPP yet, return early for non tegra20/30









	 * Tegra124+ doesn't support OPP yet, return early for pre-Tegra124









	 * case.









	 */









	if (!config.supported_hw)
































drivers/soc/tegra/pmc.c



+416
−248




























File changed.
Preview size limit exceeded, changes collapsed.